A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a low voltage CMOS process

Brendan Mullane; Vincent O'Brien

doi:10.1007/978-3-642-32770-4_9

A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a low voltage CMOS process

Brendan Mullane, Vincent O'Brien

Department of Electronics & Computer Engineering

University of Limerick

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Direct Digital Synthesis (DDS) systems generate fine frequency resolution signals over a broad spectrum that are used in a wide variety of applications such as multi-mode RF, communications, measurements and test. A high performance DDS band-pass Digital to Analog Converter (DAC) architecture and implementation is presented that delivers high spectral purity over a narrow-band response. The low power D/A Converter is portable to standard CMOS processes and designed to achieve over 100dB narrow-band SFDR performance using Sigma-Delta (ΣΔ) modulation and multi-bit current steering techniques. A 3 ^rd order digital ΣΔ modulator is combined with a 4 ^th order digital Dynamic Element Matching (DEM) block to shape the noise while calibrating for process mismatch variations. A low silicon area output stage is used to deliver a high performance specification.

Original language	English
Title of host publication	VLSI-SoC
Subtitle of host publication	Advanced Research for Systems on Chip - 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Revised Selected Papers
Pages	144-157
Number of pages	14
DOIs	https://doi.org/10.1007/978-3-642-32770-4_9
Publication status	Published - 2012
Event	19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011 - Hong Kong, China Duration: 3 Oct 2011 → 5 Oct 2011

Publication series

Name	IFIP Advances in Information and Communication Technology
Volume	379 AICT
ISSN (Print)	1868-4238

Conference

Conference	19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011
Country/Territory	China
City	Hong Kong
Period	3/10/11 → 5/10/11

Keywords

Band-Pass DAC
DDS
DEM
Digital to Analog Converter
Noise-shaping
Static Mismatch

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10.1007/978-3-642-32770-4_9

Cite this

Mullane, B., & O'Brien, V. (2012). A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a low voltage CMOS process. In VLSI-SoC: Advanced Research for Systems on Chip - 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Revised Selected Papers (pp. 144-157). (IFIP Advances in Information and Communication Technology; Vol. 379 AICT). https://doi.org/10.1007/978-3-642-32770-4_9

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Mullane, B & O'Brien, V 2012, A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a low voltage CMOS process. in VLSI-SoC: Advanced Research for Systems on Chip - 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Revised Selected Papers. IFIP Advances in Information and Communication Technology, vol. 379 AICT, pp. 144-157, 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Hong Kong, China, 3/10/11. https://doi.org/10.1007/978-3-642-32770-4_9

A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a low voltage CMOS process. / Mullane, Brendan; O'Brien, Vincent.
VLSI-SoC: Advanced Research for Systems on Chip - 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Revised Selected Papers. 2012. p. 144-157 (IFIP Advances in Information and Communication Technology; Vol. 379 AICT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Mullane B, O'Brien V. A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a low voltage CMOS process. In VLSI-SoC: Advanced Research for Systems on Chip - 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Revised Selected Papers. 2012. p. 144-157. (IFIP Advances in Information and Communication Technology). doi: 10.1007/978-3-642-32770-4_9

A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a low voltage CMOS process

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