Abstract
This paper describes a novel and highly versatile reduced Instruction set (RISC) based fixed point digital signal processor (DSP). Its architecture, Instruction set, and integrated programmable digital pulse width modulator (DPWM) have been optimized for digitally controlled switched mode power converters (SMPCs). Designed using the Verilog hardware description language (HDL), the prototype DSP integrated circuit (IC) was built on a standard 0.35 μm digital CMOS process (with a 20 K gate count). It occupies less then 1.5 mm2 and dissipates approximately 5 mW from a 3.3 V supply at 50 MIPs. The device provides a programmable and cost effective solution for digitally controlled SMPCs.
Original language | English |
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Pages | 50-56 |
Number of pages | 7 |
DOIs | |
Publication status | Published - 2005 |
Event | 20th Annual IEEEApplied Power ElectronicsConference and Exposition, APEC 2005 - Austin, TX, United States Duration: 6 Mar 2005 → 10 Mar 2005 |
Conference
Conference | 20th Annual IEEEApplied Power ElectronicsConference and Exposition, APEC 2005 |
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Country/Territory | United States |
City | Austin, TX |
Period | 6/03/05 → 10/03/05 |
Keywords
- Digital control
- Digital signal processor