A high performance band-pass DAC architecture and design targeting a low voltage silicon process

Brendan Mullane; Vincent O'Brien

doi:10.1109/VLSISoC.2011.6081601

A high performance band-pass DAC architecture and design targeting a low voltage silicon process

Brendan Mullane, Vincent O'Brien

Department of Electronics & Computer Engineering

University of Limerick

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Direct Digital Synthesis (DDS) systems generate adjustable high resolution phase and frequency signals that are used in a wide variety of applications such as multi-mode RF, communications, measurements and test. A high performance band-pass DAC architecture and implementation is presented that delivers high spectral purity over a narrow-band response. The low power DAC is portable to standard CMOS processes and achieves 110dB narrowband SFDR performance using sigma-delta (ΣΔ) modulation and multi-bit current steering techniques. A 3rd order digital ΣΔ modulator is combined with a 4th order digital Dynamic Element Matching (DEM) block to shape the noise while calibrating for process mismatch variations. A low silicon area output stage is used to deliver a high performance specification.

Original language	English
Title of host publication	2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011
Pages	325-330
Number of pages	6
DOIs	https://doi.org/10.1109/VLSISoC.2011.6081601
Publication status	Published - 2011
Event	2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011 - Kowloon, Hong Kong Duration: 3 Oct 2011 → 5 Oct 2011

Publication series

Name	2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011

Conference

Conference	2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011
Country/Territory	Hong Kong
City	Kowloon
Period	3/10/11 → 5/10/11

Keywords

Band-Pass DAC
DDS
Digital to Analog Converter
Noise-shaping DEM
Static Mismatch

Access to Document

10.1109/VLSISoC.2011.6081601

Cite this

Mullane, B., & O'Brien, V. (2011). A high performance band-pass DAC architecture and design targeting a low voltage silicon process. In 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011 (pp. 325-330). Article 6081601 (2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011). https://doi.org/10.1109/VLSISoC.2011.6081601

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title = "A high performance band-pass DAC architecture and design targeting a low voltage silicon process",

abstract = "Direct Digital Synthesis (DDS) systems generate adjustable high resolution phase and frequency signals that are used in a wide variety of applications such as multi-mode RF, communications, measurements and test. A high performance band-pass DAC architecture and implementation is presented that delivers high spectral purity over a narrow-band response. The low power DAC is portable to standard CMOS processes and achieves 110dB narrowband SFDR performance using sigma-delta (ΣΔ) modulation and multi-bit current steering techniques. A 3rd order digital ΣΔ modulator is combined with a 4th order digital Dynamic Element Matching (DEM) block to shape the noise while calibrating for process mismatch variations. A low silicon area output stage is used to deliver a high performance specification.",

keywords = "Band-Pass DAC, DDS, Digital to Analog Converter, Noise-shaping DEM, Static Mismatch",

author = "Brendan Mullane and Vincent O'Brien",

year = "2011",

doi = "10.1109/VLSISoC.2011.6081601",

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series = "2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011",

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booktitle = "2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011",

note = "2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011 ; Conference date: 03-10-2011 Through 05-10-2011",

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Mullane, B & O'Brien, V 2011, A high performance band-pass DAC architecture and design targeting a low voltage silicon process. in 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011., 6081601, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, pp. 325-330, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, 3/10/11. https://doi.org/10.1109/VLSISoC.2011.6081601

A high performance band-pass DAC architecture and design targeting a low voltage silicon process. / Mullane, Brendan; O'Brien, Vincent.
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011. 2011. p. 325-330 6081601 (2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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A high performance band-pass DAC architecture and design targeting a low voltage silicon process

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