Abstract
This research work proposes a novel fusion of the Modified Decision Tree algorithm and the Local Binary Histogram Pattern-based improved KNN algorithm to investigate fault occurrence and prediction in the switches of a multi-level inverter. This work utilizes non-carrier switching angle based
digital Pulse Width Modulation signals as switch patterns to drive a 27-level Switched Ladder type Multi-level Inverter. The improved KNN with the LBPH considers the image form of the 27-level AC output to predict the switch faults; concurrently, the modified decision tree algorithm identifies the faults from the truth table. Though there are several artificial intelligence based algorithms for fault analysis of the power inverters, the fusion of improved KNN, modified
decision tree algorithm, and local binary histogram pattern satisfies in terms of accurate prediction and identification of faults in the 27-level Trinary Switched Ladder Multi-level Inverter. For the sake of validation, the proposed fusion algorithm is implemented using a Xilinx Kintex UltraScale+ FPGA device. The parametric analysis of Latency, Cost Function, Area, and Power is
evaluated to prove the merit of the proposed algorithm. Also, the IC layout is developed for the proposed algorithm using the Cadence EDA tool.
digital Pulse Width Modulation signals as switch patterns to drive a 27-level Switched Ladder type Multi-level Inverter. The improved KNN with the LBPH considers the image form of the 27-level AC output to predict the switch faults; concurrently, the modified decision tree algorithm identifies the faults from the truth table. Though there are several artificial intelligence based algorithms for fault analysis of the power inverters, the fusion of improved KNN, modified
decision tree algorithm, and local binary histogram pattern satisfies in terms of accurate prediction and identification of faults in the 27-level Trinary Switched Ladder Multi-level Inverter. For the sake of validation, the proposed fusion algorithm is implemented using a Xilinx Kintex UltraScale+ FPGA device. The parametric analysis of Latency, Cost Function, Area, and Power is
evaluated to prove the merit of the proposed algorithm. Also, the IC layout is developed for the proposed algorithm using the Cadence EDA tool.
| Original language | English (Ireland) |
|---|---|
| Article number | 111171 |
| Pages (from-to) | 1 |
| Number of pages | 21 |
| Journal | Computers and Electrical Engineering |
| Volume | 135 |
| DOIs | |
| Publication status | Published - Jul 2026 |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 7 Affordable and Clean Energy
Keywords
- Multi-level inverter
- Fault analysis
- Local binary histogram pattern
- Improved KNN
- Modified decision tree algorithm
- Field programmable gate array
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