A new synchronizer design

Jacqueline Walker; Antonio Cantoni

doi:10.1109/12.544488

A new synchronizer design

Research output: Contribution to journal › Article › peer-review

Abstract

A new synchronizer design is presented. Current synchronizer designs have certain disadvantages, both in characterization and in the tradeoff between settling time and sampling rate, which are overcome in the new design. Two possible implementations of the synchronizer are discussed.

Original language	English
Pages (from-to)	1308-1311
Number of pages	4
Journal	IEEE Transactions on Computers
Volume	45
Issue number	11
DOIs	https://doi.org/10.1109/12.544488
Publication status	Published - 1996
Externally published	Yes

Keywords

Asynchronous
Flip-flop
Metastability
Synchronization
Synchronizer
Synchronizer design
Synchronous digital systems

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10.1109/12.544488

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title = "A new synchronizer design",

abstract = "A new synchronizer design is presented. Current synchronizer designs have certain disadvantages, both in characterization and in the tradeoff between settling time and sampling rate, which are overcome in the new design. Two possible implementations of the synchronizer are discussed.",

keywords = "Asynchronous, Flip-flop, Metastability, Synchronization, Synchronizer, Synchronizer design, Synchronous digital systems",

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year = "1996",

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KW - Flip-flop

KW - Metastability

KW - Synchronization

KW - Synchronizer

KW - Synchronizer design

KW - Synchronous digital systems

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A new synchronizer design

Abstract

Keywords

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