TY - GEN
T1 - A novel digital single-wire quasi-democratic stress share scheme for paralleled switching converters
AU - Rinne, Karl
AU - Kelly, Anthony
AU - O'Malley, Eamon
PY - 2010
Y1 - 2010
N2 - A novel Digital Stress Share (DSS) scheme, useful for paralleled switch-mode power converters (SMPCs), is presented. Due to its unique feature set DSS lends itself particularly well to modern power architectures where load currents (or - more generically - converter stresses) need to be actively balanced between an arbitrary number of digitally controlled DC-DC switching converters. The DSS scheme is suitable for single-wire implementation offering a low-cost and robust platform. DSS is master-less and quasi-democratic, eliminating all known drawbacks of analog current share lines, and offering significant improvements over competing digital current share methods. It features inter-device stress share communication with fully predictable timing, regardless of the number of SMPCs working in parallel. Data throughput as well as data storage requirements are minimized. Measurement results confirm excellent stress share performance under various operating conditions. The DSS scheme is versatile, robust, fault-tolerant and scalable. DSS defines an electrical bus interface, as well as an isochronous protocol.
AB - A novel Digital Stress Share (DSS) scheme, useful for paralleled switch-mode power converters (SMPCs), is presented. Due to its unique feature set DSS lends itself particularly well to modern power architectures where load currents (or - more generically - converter stresses) need to be actively balanced between an arbitrary number of digitally controlled DC-DC switching converters. The DSS scheme is suitable for single-wire implementation offering a low-cost and robust platform. DSS is master-less and quasi-democratic, eliminating all known drawbacks of analog current share lines, and offering significant improvements over competing digital current share methods. It features inter-device stress share communication with fully predictable timing, regardless of the number of SMPCs working in parallel. Data throughput as well as data storage requirements are minimized. Measurement results confirm excellent stress share performance under various operating conditions. The DSS scheme is versatile, robust, fault-tolerant and scalable. DSS defines an electrical bus interface, as well as an isochronous protocol.
UR - http://www.scopus.com/inward/record.url?scp=77952139304&partnerID=8YFLogxK
U2 - 10.1109/APEC.2010.5433652
DO - 10.1109/APEC.2010.5433652
M3 - Conference contribution
AN - SCOPUS:77952139304
SN - 9781424447824
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 328
EP - 335
BT - APEC 2010 - 25th Annual IEEE Applied Power Electronics Conference and Exposition
T2 - 25th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2010
Y2 - 21 February 2010 through 25 February 2010
ER -