TY - GEN
T1 - A novel system on chip (SoC) test solution
AU - Higgins, Michael
AU - MacNamee, Ciaran
AU - Mullane, Brendan
PY - 2008
Y1 - 2008
N2 - A novel test controller architecture is presented that allows multiple IEEE 1500 wrapped cores within a SoC to be tested concurrently. The IEEE 1149.1 state machine is used to interface to the test controller allowing potential integration with the emerging IEEE P1687 (IJTAG) standard. Also included is a Test Access Mechanism (TAM) methodology that reuses the physical connections of the SoC system bus to provide an efficient transport medium for test vectors between the test controller and IEEE 1500 wrapped cores.
AB - A novel test controller architecture is presented that allows multiple IEEE 1500 wrapped cores within a SoC to be tested concurrently. The IEEE 1149.1 state machine is used to interface to the test controller allowing potential integration with the emerging IEEE P1687 (IJTAG) standard. Also included is a Test Access Mechanism (TAM) methodology that reuses the physical connections of the SoC system bus to provide an efficient transport medium for test vectors between the test controller and IEEE 1500 wrapped cores.
UR - http://www.scopus.com/inward/record.url?scp=51849164109&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2008.36
DO - 10.1109/ISVLSI.2008.36
M3 - Conference contribution
AN - SCOPUS:51849164109
SN - 9780769531700
T3 - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008
SP - 145
EP - 150
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI
T2 - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008
Y2 - 7 April 2008 through 9 April 2008
ER -