TY - GEN
T1 - A prototype platform for system-on-chip ADC test and measurement
AU - Mullane, Brendan
AU - O'Brien, Vincent
AU - MacNamee, Ciaran
AU - Fleischmann, Thomas
PY - 2009
Y1 - 2009
N2 - An optimal solution for implementing ADC Built-In-Self-Test into a SOC design is presented. ADC linear and dynamic testing occurs in parallel which reduces test time. A signal generator produces a ramp for linear histogram measurements and a sinewave signal for dynamic tests. This platform permits a BIST design that is predominantly a digital solution and enables accurate testing using low silicon area
AB - An optimal solution for implementing ADC Built-In-Self-Test into a SOC design is presented. ADC linear and dynamic testing occurs in parallel which reduces test time. A signal generator produces a ramp for linear histogram measurements and a sinewave signal for dynamic tests. This platform permits a BIST design that is predominantly a digital solution and enables accurate testing using low silicon area
UR - http://www.scopus.com/inward/record.url?scp=77949604257&partnerID=8YFLogxK
U2 - 10.1109/SOCCON.2009.5398065
DO - 10.1109/SOCCON.2009.5398065
M3 - Conference contribution
AN - SCOPUS:77949604257
SN - 9781424452200
T3 - Proceedings - IEEE International SOC Conference, SOCC 2009
SP - 169
EP - 172
BT - Proceedings - IEEE International SOC Conference, SOCC 2009
T2 - IEEE International SOC Conference, SOCC 2009
Y2 - 9 September 2009 through 11 September 2009
ER -