A Reduced Hardware ISI and Mismatch Shaping DEM Decoder

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a dynamic element matching (DEM) decoder incorporating both intersymbol interference (ISI) and mismatch error shaping. From the analysis of ISI error in multi-bit DACs, an algorithm is developed that deterministically controls the element transitions, such that on each conversion cycle the instantaneous number of on transitions is set to a constant value, while the instantaneous number of off transitions varies with the decoder input signal. The technique achieves greater ISI error mitigation than previous approaches using less hardware. To further reduce the logic area, a hierarchical DEM structure, whereby the DEM decoder is split into multiple sub-DEM decoders, is presented.

Original languageEnglish
Pages (from-to)2299-2317
Number of pages19
JournalCircuits, Systems, and Signal Processing
Volume37
Issue number6
DOIs
Publication statusPublished - 1 Jun 2018

Keywords

  • Delta sigma
  • Digital-to-analog converter (DAC)
  • Dynamic element matching (DEM)
  • Element selection logic (ESL)
  • Intersymbol interference (ISI)

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