TY - JOUR
T1 - A Reduced Hardware ISI and Mismatch Shaping DEM Decoder
AU - O’Brien, Vincent
AU - Scanlan, Anthony G.
AU - Mullane, Brendan
N1 - Publisher Copyright:
© 2017, Springer Science+Business Media, LLC.
PY - 2018/6/1
Y1 - 2018/6/1
N2 - This paper presents a dynamic element matching (DEM) decoder incorporating both intersymbol interference (ISI) and mismatch error shaping. From the analysis of ISI error in multi-bit DACs, an algorithm is developed that deterministically controls the element transitions, such that on each conversion cycle the instantaneous number of on transitions is set to a constant value, while the instantaneous number of off transitions varies with the decoder input signal. The technique achieves greater ISI error mitigation than previous approaches using less hardware. To further reduce the logic area, a hierarchical DEM structure, whereby the DEM decoder is split into multiple sub-DEM decoders, is presented.
AB - This paper presents a dynamic element matching (DEM) decoder incorporating both intersymbol interference (ISI) and mismatch error shaping. From the analysis of ISI error in multi-bit DACs, an algorithm is developed that deterministically controls the element transitions, such that on each conversion cycle the instantaneous number of on transitions is set to a constant value, while the instantaneous number of off transitions varies with the decoder input signal. The technique achieves greater ISI error mitigation than previous approaches using less hardware. To further reduce the logic area, a hierarchical DEM structure, whereby the DEM decoder is split into multiple sub-DEM decoders, is presented.
KW - Delta sigma
KW - Digital-to-analog converter (DAC)
KW - Dynamic element matching (DEM)
KW - Element selection logic (ESL)
KW - Intersymbol interference (ISI)
UR - http://www.scopus.com/inward/record.url?scp=85045977543&partnerID=8YFLogxK
U2 - 10.1007/s00034-017-0681-8
DO - 10.1007/s00034-017-0681-8
M3 - Article
AN - SCOPUS:85045977543
SN - 0278-081X
VL - 37
SP - 2299
EP - 2317
JO - Circuits, Systems, and Signal Processing
JF - Circuits, Systems, and Signal Processing
IS - 6
ER -