A study on the effect of test vector randomness on test length and its fault coverage

Muhammad Sadiq Sahari, Abu Khari A'Ain, Ian Grout

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a study on the impact of test sequence randomness and the fault coverage (FC) it could produce through the use of a modified structure of the conventional linear feedback shift register (LFSR). By using double input signals, the modified LFSR can control the number of test patterns generated and also prevents the sequences from being stuck in all zeroes state. Fault simulations on ISCAS'85 benchmark circuits show that a high FC for combinational logic circuits has been obtained. Another observation is that the modified structure could achieve high FC with a smaller test sequence compared to other reported test pattern generation (TPG) techniques.

Original languageEnglish
Title of host publication2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings
Pages503-506
Number of pages4
DOIs
Publication statusPublished - 2012
Event2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Kuala Lumpur, Malaysia
Duration: 19 Sep 201221 Sep 2012

Publication series

Name2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings

Conference

Conference2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012
Country/TerritoryMalaysia
CityKuala Lumpur
Period19/09/1221/09/12

Fingerprint

Dive into the research topics of 'A study on the effect of test vector randomness on test length and its fault coverage'. Together they form a unique fingerprint.

Cite this