@inproceedings{3f30cae070c5474fb224686f06f869c7,
title = "A Tri-level Current-Steering DAC Design with Improved Output-Impedance Related Dynamic Performance",
abstract = "This paper presents a design of a low-latency 12-bit linear tri-level current-steering digital-to-analogue-converter for use in continuous-time ADCs. The DAC design achieves 12-bit static linearity, while the combination of DAC slice impedance matching with a proposed compensation technique reduces output-impedance related distortion. The technique demonstrates 10dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/$s$. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.",
keywords = "Current-Steering, DAC, HD3, SFDR, Tri-level",
author = "Shantanu Mehta and Scanlan, {Anthony G.} and Brendan Mullane and Daniel O'Hare",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 17th IEEE International New Circuits and Systems Conference, NEWCAS 2019 ; Conference date: 23-06-2019 Through 26-06-2019",
year = "2019",
month = jun,
doi = "10.1109/NEWCAS44328.2019.8961257",
language = "English",
series = "17th IEEE International New Circuits and Systems Conference, NEWCAS 2019",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "17th IEEE International New Circuits and Systems Conference, NEWCAS 2019",
}