A Tri-level Current-Steering DAC Design with Improved Output-Impedance Related Dynamic Performance

Shantanu Mehta, Anthony G. Scanlan, Brendan Mullane, Daniel O'Hare

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a design of a low-latency 12-bit linear tri-level current-steering digital-to-analogue-converter for use in continuous-time ADCs. The DAC design achieves 12-bit static linearity, while the combination of DAC slice impedance matching with a proposed compensation technique reduces output-impedance related distortion. The technique demonstrates 10dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/$s$. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.

Original languageEnglish
Title of host publication17th IEEE International New Circuits and Systems Conference, NEWCAS 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728110318
DOIs
Publication statusPublished - Jun 2019
Event17th IEEE International New Circuits and Systems Conference, NEWCAS 2019 - Munich, Germany
Duration: 23 Jun 201926 Jun 2019

Publication series

Name17th IEEE International New Circuits and Systems Conference, NEWCAS 2019

Conference

Conference17th IEEE International New Circuits and Systems Conference, NEWCAS 2019
Country/TerritoryGermany
CityMunich
Period23/06/1926/06/19

Keywords

  • Current-Steering
  • DAC
  • HD3
  • SFDR
  • Tri-level

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