TY - JOUR
T1 - An approach to realistic fault prediction and layout design for testability in analog circuits
AU - Prieto, J. A.
AU - Rueda, A.
AU - Grout, I.
AU - Peralias, E.
AU - Huertas, J. L.
AU - Richardson, A. M.D.
PY - 1998
Y1 - 1998
N2 - This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability.
AB - This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability.
UR - http://www.scopus.com/inward/record.url?scp=33750080236&partnerID=8YFLogxK
U2 - 10.1109/DATE.1998.655965
DO - 10.1109/DATE.1998.655965
M3 - Conference article
AN - SCOPUS:33750080236
SN - 1530-1591
SP - 905
EP - 909
JO - Proceedings -Design, Automation and Test in Europe, DATE
JF - Proceedings -Design, Automation and Test in Europe, DATE
M1 - 655965
T2 - Design, Automation and Test in Europe, DATE 1998
Y2 - 23 February 1998 through 26 February 1998
ER -