@inproceedings{9c9c471ecb684a7981d93f4face05cfd,
title = "An FPGA based reconfigurable IPSec ESP core suitable for IoT applications",
abstract = "This work implements an FPGA (Field Programmable Gate Array) based reconfigurable IPSec ESP core. The IPSec protocol, developed by the IETF (Internet Engineering Task Force) in 1998, is a popular solution to facilitate protection of the data being transferred at the IP layer. IPSec ESP is one of the two main IPSec protocols (AH: Authentication Header and ESP: Encapsulation Security Payload). IPSec ESP is used to provide data confidentiality security services with Authenticity (optional). Implementation of the IPSec is a computing intensive work, that's why hardware implementation of IPSec is a best solution. Here, to design IPSec ESP core an encryption algorithm AES is used. Proposed design also supports ESP-tunnel and ESP-transport mode of operation. This core is tested by applying default length of 576 bytes for an IPv4 datagram and results are reported on Virtex-5 and Virtex-6 FPGAs. The proposed IPSec ESP core can be used to provide data confidentiality security to IoT applications.",
keywords = "AES, ESP, FPGA, IPSec",
author = "Muzaffar Rao and Joseph Coleman and Thomas Newe",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 10th International Conference on Sensing Technology, ICST 2016 ; Conference date: 11-11-2016 Through 13-11-2016",
year = "2016",
month = dec,
day = "22",
doi = "10.1109/ICSensT.2016.7796269",
language = "English",
series = "Proceedings of the International Conference on Sensing Technology, ICST",
publisher = "IEEE Computer Society",
booktitle = "2016 10th International Conference on Sensing Technology, ICST 2016",
}