An in-place processor design for real-value FFTs targeting in-situ dynamic ADC test

Brendan Mullane; Vincent O'Brien

doi:10.1109/MWSCAS.2018.8623967

An in-place processor design for real-value FFTs targeting in-situ dynamic ADC test

Brendan Mullane, Vincent O'Brien

Department of Electronics & Computer Engineering

University of Limerick

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a processor architecture for Fast Fourier Transform computation of real-valued signals for on-chip analog to digital converter test and evaluation. The design performs a radix-2 technique optimized for low area overhead and easy integration into system on chips. The hardware logic supports variable transform lengths and accurate parameter extraction. The processor has been validated on 0.18um CMOS silicon and applied to a data converter test application for extraction of dynamic parameters that are SINAD, SFDR and THD. The architecture is suitable for safety-critical applications where spectral integrity of the converter signal path can be run at start-up or during interval down times.

Original language	English
Title of host publication	2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	591-594
Number of pages	4
ISBN (Electronic)	9781538673928
DOIs	https://doi.org/10.1109/MWSCAS.2018.8623967
Publication status	Published - 2 Jul 2018
Event	61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 - Windsor, Canada Duration: 5 Aug 2018 → 8 Aug 2018

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	2018-August
ISSN (Print)	1548-3746

Conference

Conference	61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Country/Territory	Canada
City	Windsor
Period	5/08/18 → 8/08/18

Keywords

Fast Fourier Transform (FFT)
Analog to Digital Converter (ADC)
Built-In-Self-Test (BIST)
CORDIC
In-place
Real Value Fast Fourier Transform (RFFT)

Access to Document

10.1109/MWSCAS.2018.8623967

Cite this

Mullane, B., & O'Brien, V. (2018). An in-place processor design for real-value FFTs targeting in-situ dynamic ADC test. In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018 (pp. 591-594). Article 8623967 (Midwest Symposium on Circuits and Systems; Vol. 2018-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.2018.8623967

@inproceedings{09a40652a2cd4bc9a9e1244a7628097b,

title = "An in-place processor design for real-value FFTs targeting in-situ dynamic ADC test",

abstract = "This paper presents a processor architecture for Fast Fourier Transform computation of real-valued signals for on-chip analog to digital converter test and evaluation. The design performs a radix-2 technique optimized for low area overhead and easy integration into system on chips. The hardware logic supports variable transform lengths and accurate parameter extraction. The processor has been validated on 0.18um CMOS silicon and applied to a data converter test application for extraction of dynamic parameters that are SINAD, SFDR and THD. The architecture is suitable for safety-critical applications where spectral integrity of the converter signal path can be run at start-up or during interval down times.",

keywords = "Fast Fourier Transform (FFT), Analog to Digital Converter (ADC), Built-In-Self-Test (BIST), CORDIC, In-place, Real Value Fast Fourier Transform (RFFT)",

author = "Brendan Mullane and Vincent O'Brien",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE; 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 ; Conference date: 05-08-2018 Through 08-08-2018",

year = "2018",

month = jul,

day = "2",

doi = "10.1109/MWSCAS.2018.8623967",

language = "English",

series = "Midwest Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "591--594",

booktitle = "2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018",

}

Mullane, B & O'Brien, V 2018, An in-place processor design for real-value FFTs targeting in-situ dynamic ADC test. in 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018., 8623967, Midwest Symposium on Circuits and Systems, vol. 2018-August, Institute of Electrical and Electronics Engineers Inc., pp. 591-594, 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, Canada, 5/08/18. https://doi.org/10.1109/MWSCAS.2018.8623967

An in-place processor design for real-value FFTs targeting in-situ dynamic ADC test. / Mullane, Brendan; O'Brien, Vincent.
2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 591-594 8623967 (Midwest Symposium on Circuits and Systems; Vol. 2018-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An in-place processor design for real-value FFTs targeting in-situ dynamic ADC test

AU - Mullane, Brendan

AU - O'Brien, Vincent

PY - 2018/7/2

Y1 - 2018/7/2

N2 - This paper presents a processor architecture for Fast Fourier Transform computation of real-valued signals for on-chip analog to digital converter test and evaluation. The design performs a radix-2 technique optimized for low area overhead and easy integration into system on chips. The hardware logic supports variable transform lengths and accurate parameter extraction. The processor has been validated on 0.18um CMOS silicon and applied to a data converter test application for extraction of dynamic parameters that are SINAD, SFDR and THD. The architecture is suitable for safety-critical applications where spectral integrity of the converter signal path can be run at start-up or during interval down times.

AB - This paper presents a processor architecture for Fast Fourier Transform computation of real-valued signals for on-chip analog to digital converter test and evaluation. The design performs a radix-2 technique optimized for low area overhead and easy integration into system on chips. The hardware logic supports variable transform lengths and accurate parameter extraction. The processor has been validated on 0.18um CMOS silicon and applied to a data converter test application for extraction of dynamic parameters that are SINAD, SFDR and THD. The architecture is suitable for safety-critical applications where spectral integrity of the converter signal path can be run at start-up or during interval down times.

KW - Fast Fourier Transform (FFT)

KW - Analog to Digital Converter (ADC)

KW - Built-In-Self-Test (BIST)

KW - CORDIC

KW - In-place

KW - Real Value Fast Fourier Transform (RFFT)

UR - http://www.scopus.com/inward/record.url?scp=85062237166&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS.2018.8623967

DO - 10.1109/MWSCAS.2018.8623967

M3 - Conference contribution

AN - SCOPUS:85062237166

T3 - Midwest Symposium on Circuits and Systems

SP - 591

EP - 594

BT - 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018

Y2 - 5 August 2018 through 8 August 2018

ER -

An in-place processor design for real-value FFTs targeting in-situ dynamic ADC test

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this