An on-chip solution for static adc test and measurement

Brendan Mullane, Ciaran MacNamee, Vincent O'Brien, Thomas Fleischmann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a solution for implementing low-cost ADC BIST into a System-on-Chip design. The solution is based on generating a programmable ramp as a test signal into the ADC and measuring the linear parameters using the histogram based test. An original approach for accurately measuring the Hits-per-Code as the ramp traverses the ADC transfer curve is presented. In particular, it is shown that code transitions or code flicker noise have an impact on the overall accuracy. This test procedure permits a ramp generator implementation and test engine design that is predominantly a digital solution. Results demonstrate lower silicon area overheads and lower test time capability.

Original languageEnglish
Title of host publicationGLSVLSI 2009 - Proceedings of the 2009 Great Lakes Symposium on VLSI
Pages81-86
Number of pages6
DOIs
Publication statusPublished - 2009
Event19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09 - Boston, MA, United States
Duration: 10 May 200912 May 2009

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09
Country/TerritoryUnited States
CityBoston, MA
Period10/05/0912/05/09

Keywords

  • ADC-BIST
  • Analog to digital converter
  • Code histogram
  • Linearity measurements
  • System-on-chip
  • Test

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