An optimal IEEE 1500 core wrapper design for improved test access and reduced test time

B. Mullane, M. Higgins, C. MacNamee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

IEEE 1500 test wrappers that enable higher test bandwidth capability, system bus connectivity and efficient test vector organization are presented. Embedded core wrappers and test vectors that seamlessly work with ASIC and FPGA design flows are illustrated. Implementation and test-chip design show the positive impact on test time with potential for minimal wiring and logic overhead savings.

Original languageEnglish
Title of host publicationIET Irish Signals and Systems Conference, ISSC 2008
Pages204-209
Number of pages6
Edition539 CP
DOIs
Publication statusPublished - 2008
EventIET Irish Signals and Systems Conference, ISSC 2008 - Galway, Ireland
Duration: 18 Jun 200819 Jun 2008

Publication series

NameIET Conference Publications
Number539 CP

Conference

ConferenceIET Irish Signals and Systems Conference, ISSC 2008
Country/TerritoryIreland
CityGalway
Period18/06/0819/06/08

Keywords

  • ASIC
  • Core test
  • DFT
  • FPGA prototyping
  • IEEE 1500
  • SoC test

Fingerprint

Dive into the research topics of 'An optimal IEEE 1500 core wrapper design for improved test access and reduced test time'. Together they form a unique fingerprint.

Cite this