@inproceedings{656a8b25b7c54b659394a29d83f08ce3,
title = "An optimal IEEE 1500 core wrapper design for improved test access and reduced test time",
abstract = "IEEE 1500 test wrappers that enable higher test bandwidth capability, system bus connectivity and efficient test vector organization are presented. Embedded core wrappers and test vectors that seamlessly work with ASIC and FPGA design flows are illustrated. Implementation and test-chip design show the positive impact on test time with potential for minimal wiring and logic overhead savings.",
keywords = "ASIC, Core test, DFT, FPGA prototyping, IEEE 1500, SoC test",
author = "B. Mullane and M. Higgins and C. MacNamee",
year = "2008",
doi = "10.1049/cp:20080663",
language = "English",
isbn = "9780863419317",
series = "IET Conference Publications",
number = "539 CP",
pages = "204--209",
booktitle = "IET Irish Signals and Systems Conference, ISSC 2008",
edition = "539 CP",
note = "IET Irish Signals and Systems Conference, ISSC 2008 ; Conference date: 18-06-2008 Through 19-06-2008",
}