An SOC platform for ADC test and measurement

Brendan Mullane, Vincent O'Brien, Ciaran MacNamee, Thomas Fleischmann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An Analog to Digital Converter Built-in-Self-Test design for System-on-Chip applications is presented. Linear and dynamic ADC test occur in parallel to reduce overall test time. A ramp generator is used for linear histogram measurements and a sine-wave signal is applied for dynamic tests. The design precisely measures Hits-per-Code enabling accurate linearity test and a low-area optimal CPU operates dynamic measurements. Results demonstrate efficient silicon area overheads and lower test time capability.

Original languageEnglish
Title of host publicationProceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009
Pages4-7
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009 - Liberec, Czech Republic
Duration: 15 Apr 200917 Apr 2009

Publication series

NameProceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009

Conference

Conference2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009
Country/TerritoryCzech Republic
CityLiberec
Period15/04/0917/04/09

Keywords

  • ADC testing
  • BIST
  • Component
  • DFT
  • Dynamic test
  • Linearity test
  • System-on-chip

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