TY - GEN
T1 - Automatic multi-phase digital pulse width modulator
AU - Effler, Simon
AU - Halton, Mark
AU - Rinne, Karl
PY - 2010
Y1 - 2010
N2 - Current demands on switched-mode power supplies to deliver higher output power with improved efficiency are leading to an increased use of multi-phase power converters. With an increasing number of phases, special multi-phase digital pulse width modulators (DPWMs) prove advantageous over the parallel use of conventional DPWMs. In this paper a "smart" multi-phase DPWM is presented which incorporates a duty cycle distribution algorithm. This algorithm is based on the fastest execution of the duty cycle input command with respect to the number of switching actions per phase and switching cycle. The system provides good dynamic current sharing during transients and enables the use of "faster" digital loop compensators. Intrinsic support of a variable number of active phases (phaseshedding operation) and improved scalability over conventional designs complete the feature set. The proposed system has been implemented on an FPGA system and tested with a four-phase buck converter.
AB - Current demands on switched-mode power supplies to deliver higher output power with improved efficiency are leading to an increased use of multi-phase power converters. With an increasing number of phases, special multi-phase digital pulse width modulators (DPWMs) prove advantageous over the parallel use of conventional DPWMs. In this paper a "smart" multi-phase DPWM is presented which incorporates a duty cycle distribution algorithm. This algorithm is based on the fastest execution of the duty cycle input command with respect to the number of switching actions per phase and switching cycle. The system provides good dynamic current sharing during transients and enables the use of "faster" digital loop compensators. Intrinsic support of a variable number of active phases (phaseshedding operation) and improved scalability over conventional designs complete the feature set. The proposed system has been implemented on an FPGA system and tested with a four-phase buck converter.
UR - http://www.scopus.com/inward/record.url?scp=77952192481&partnerID=8YFLogxK
U2 - 10.1109/APEC.2010.5433369
DO - 10.1109/APEC.2010.5433369
M3 - Conference contribution
AN - SCOPUS:77952192481
SN - 9781424447824
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 1087
EP - 1092
BT - APEC 2010 - 25th Annual IEEE Applied Power Electronics Conference and Exposition
T2 - 25th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2010
Y2 - 21 February 2010 through 25 February 2010
ER -