AVERT: An Automatic Verilog Testbench Generation Tool for Grammatical Evolution

With the ever-growing complexity of digital circuits, the appeal of using Machine Learning in digital circuit design has grown significantly. Over the last 25 years, Evolutionary Algorithms have been used to create digital circuits in a field known as Evolutionary Hardware (EH). Using Hardware Description Languages (HDLs) in EH is an attractive prospect as the evolved circuits would be easy to understand and simple to integrate with existing IP designs. However, one limitation of this method is that a testbench must be created by hand to check the Device Under Testing's (DUT) functionality, increasing the preparatory work required to evolve a new design. This paper presents AVERT, an Automatic Verilog Testbench Generation Tool for Grammatical Evolution. By specifying the connection ports of the DUT and the test vectors (test cases) in a standard test vector file, we describe a system that allows a testbench to be generated for sequential and combinational designs written in both structural and behavioural modelling styles. We take three problems from the literature and successfully evolve candidate solutions for each problem. Experimental results show a significant improvement in simulation performance by evaluating multiple DUTs per testbench compared to a single DUT per testbench.