Bandwidth enhancement to continuous-time input pipeline ADCs

Daniel O’Hare; Anthony G. Scanlan; Eric Thompson; Brendan Mullane

doi:10.1109/TVLSI.2017.2763129

Bandwidth enhancement to continuous-time input pipeline ADCs

Daniel O’Hare, Anthony G. Scanlan, Eric Thompson, Brendan Mullane

Research output: Contribution to journal › Article › peer-review

Abstract

—This paper presents design analysis and insights for a new continuous-time input pipeline (CTIP) analog-to-digital converter (ADC) architecture that has enhanced bandwidth. An all-pass filter-based analog delay in the signal path allows bandwidth extension to Nyquist signal bandwidths. A resetting integrator gain stage provides a signal path delay helping to increase the bandwidth while reducing the power cost. The noise filtering property of the resetting integrator gain stage preserves the medium resistive input benefit of CTIP ADCs. The resetting integrator allows the architecture to be implemented with a feedforward compensated op-amp using low-voltage CMOS processes. This paper has been verified by simulation results of a CTIP ADC with 1.2-V supply voltage designed in TSMC’s 65-nm CMOS technology.

Original language	English
Article number	8091299
Pages (from-to)	404-415
Number of pages	12
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	26
Issue number	2
DOIs	https://doi.org/10.1109/TVLSI.2017.2763129
Publication status	Published - Feb 2018

Keywords

Analog-to-digital conversion
Antialias filter
CMOS analog integrated circuits
Continuous time (CT)
Pipeline

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10.1109/TVLSI.2017.2763129

Cite this

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title = "Bandwidth enhancement to continuous-time input pipeline ADCs",

abstract = "—This paper presents design analysis and insights for a new continuous-time input pipeline (CTIP) analog-to-digital converter (ADC) architecture that has enhanced bandwidth. An all-pass filter-based analog delay in the signal path allows bandwidth extension to Nyquist signal bandwidths. A resetting integrator gain stage provides a signal path delay helping to increase the bandwidth while reducing the power cost. The noise filtering property of the resetting integrator gain stage preserves the medium resistive input benefit of CTIP ADCs. The resetting integrator allows the architecture to be implemented with a feedforward compensated op-amp using low-voltage CMOS processes. This paper has been verified by simulation results of a CTIP ADC with 1.2-V supply voltage designed in TSMC{\textquoteright}s 65-nm CMOS technology.",

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AU - Scanlan, Anthony G.

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Bandwidth enhancement to continuous-time input pipeline ADCs

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