Behavioural modelling of digital circuits in system Verilog using grammatical evolution

Conor Ryan, Michael Kwaku Tetteh, Douglas Mota Dias

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Digital circuit design is an immensely complex and time consuming task that has been aided greatly by the use of Hardware Description Languages and powerful digital circuit simulators that permit a designer to program at a much higher level of abstraction, similar to how software programmers now rarely use Assembly Language, and also to test their circuits before committing them to hardware. We introduce Automatic Design of Digital Circuits (ADDC), a system comprised of Grammatical Evolution (GE), System Verilog, a high level Hardware Description Language (HDL) and Icarus, a powerful, but freely available, digital circuit simulator. ADDC operates at a much higher level than previous digital circuit evolution due to the fact that System Verilog supports behavioural modelling through the use of high level constructs such as If-Then-Else, Case and Always procedural blocks. Not only are HDLs very expressive, but they are also far more understandable than circuit diagrams, so solutions produced by ADDC are quite interpretable by humans. ADDC is applied to three benchmark problems from the Digital Circuit Literature. We show that ADDC is successful on all three benchmarks and further demonstrate how the integration of simple knowledge, e.g. the separation of input and output wires, is feasible through the grammars, and can have a major impact on overall performance.

Original languageEnglish
Title of host publicationIJCCI 2020 - Proceedings of the 12th International Joint Conference on Computational Intelligence
EditorsJuan Julian Merelo, Jonathan Garibaldi, Christian Wagner, Thomas Back, Kurosh Madani, Kevin Warwick
PublisherSciTePress
Pages28-39
Number of pages12
ISBN (Electronic)9789897584756
ISBN (Print)9789897584756
DOIs
Publication statusPublished - 2020
Event12th International Joint Conference on Computational Intelligence, IJCCI 2020 - Virtual, Online
Duration: 2 Nov 20204 Nov 2020

Publication series

NameInternational Joint Conference on Computational Intelligence
Volume1
ISSN (Electronic)2184-3236

Conference

Conference12th International Joint Conference on Computational Intelligence, IJCCI 2020
CityVirtual, Online
Period2/11/204/11/20

Keywords

  • Digital circuit design
  • Evolvable hardware
  • Grammatical evolution
  • Hardware Description Languages (HDL)
  • Lexicase selection

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