TY - GEN
T1 - Behavioural modelling of digital circuits in system Verilog using grammatical evolution
AU - Ryan, Conor
AU - Tetteh, Michael Kwaku
AU - Dias, Douglas Mota
N1 - Publisher Copyright:
Copyright © 2020 by SCITEPRESS - Science and Technology Publications, Lda. All rights reserved
PY - 2020
Y1 - 2020
N2 - Digital circuit design is an immensely complex and time consuming task that has been aided greatly by the use of Hardware Description Languages and powerful digital circuit simulators that permit a designer to program at a much higher level of abstraction, similar to how software programmers now rarely use Assembly Language, and also to test their circuits before committing them to hardware. We introduce Automatic Design of Digital Circuits (ADDC), a system comprised of Grammatical Evolution (GE), System Verilog, a high level Hardware Description Language (HDL) and Icarus, a powerful, but freely available, digital circuit simulator. ADDC operates at a much higher level than previous digital circuit evolution due to the fact that System Verilog supports behavioural modelling through the use of high level constructs such as If-Then-Else, Case and Always procedural blocks. Not only are HDLs very expressive, but they are also far more understandable than circuit diagrams, so solutions produced by ADDC are quite interpretable by humans. ADDC is applied to three benchmark problems from the Digital Circuit Literature. We show that ADDC is successful on all three benchmarks and further demonstrate how the integration of simple knowledge, e.g. the separation of input and output wires, is feasible through the grammars, and can have a major impact on overall performance.
AB - Digital circuit design is an immensely complex and time consuming task that has been aided greatly by the use of Hardware Description Languages and powerful digital circuit simulators that permit a designer to program at a much higher level of abstraction, similar to how software programmers now rarely use Assembly Language, and also to test their circuits before committing them to hardware. We introduce Automatic Design of Digital Circuits (ADDC), a system comprised of Grammatical Evolution (GE), System Verilog, a high level Hardware Description Language (HDL) and Icarus, a powerful, but freely available, digital circuit simulator. ADDC operates at a much higher level than previous digital circuit evolution due to the fact that System Verilog supports behavioural modelling through the use of high level constructs such as If-Then-Else, Case and Always procedural blocks. Not only are HDLs very expressive, but they are also far more understandable than circuit diagrams, so solutions produced by ADDC are quite interpretable by humans. ADDC is applied to three benchmark problems from the Digital Circuit Literature. We show that ADDC is successful on all three benchmarks and further demonstrate how the integration of simple knowledge, e.g. the separation of input and output wires, is feasible through the grammars, and can have a major impact on overall performance.
KW - Digital circuit design
KW - Evolvable hardware
KW - Grammatical evolution
KW - Hardware Description Languages (HDL)
KW - Lexicase selection
UR - http://www.scopus.com/inward/record.url?scp=85107287769&partnerID=8YFLogxK
U2 - 10.5220/0010066600280039
DO - 10.5220/0010066600280039
M3 - Conference contribution
AN - SCOPUS:85107287769
SN - 9789897584756
T3 - International Joint Conference on Computational Intelligence
SP - 28
EP - 39
BT - IJCCI 2020 - Proceedings of the 12th International Joint Conference on Computational Intelligence
A2 - Merelo, Juan Julian
A2 - Garibaldi, Jonathan
A2 - Wagner, Christian
A2 - Back, Thomas
A2 - Madani, Kurosh
A2 - Warwick, Kevin
PB - SciTePress
T2 - 12th International Joint Conference on Computational Intelligence, IJCCI 2020
Y2 - 2 November 2020 through 4 November 2020
ER -