Behavioural Modelling of Digital Circuits in SystemVerilog Using Grammatical Evolution

Digital circuit design is a very complex and time consuming task which requires a great deal of skill. It has been greatly aided by the use of Hardware Description Languages (HDLs) and powerful logic simulators. HDLs permit circuit designers to design circuits at a very abstract level. These are then tested before being committed to hardware. We present Automatic Design of Digital Circuits (ADDC), a system that employs Grammatical Evolution, SystemVerilog (an HDL) and Icarus Verilog (simulator) to design conventional circuits. ADDC is easily configurable to use with different HDLs and logic simulators. ADDC designs circuits at a higher abstraction level compared with previous works due to the use of HDLs, which are very expressive. Constructs such as if-else, always procedural block, generate for-loop (or synthesizable for-loop) and switch-case are readily available aiding designers to behaviourally describe circuits. In addition, due to the expressiveness of HDLs, ADDC evolved solutions are quite human interpretable. ADDC is tested using three combinational and two sequential circuits. We show that ADDC is successful on all five benchmark problems. In addition, we show that the introduction of simple domain knowledge into grammars has a major impact on evolutionary performance. Furthermore, Probabilisitc Tree Creation 2 initialization routine performed better on most digital circuit benchmark problems but not all compared to Sensible Initialization.