BIST Design and Implementation for a Fixed-Point Arithmetic MAC Unit within a Systolic Array

In embedded systems involving hardware accelerators to support embedded machine learning (ML) applications, both sequential and parallel operations are used to ensure the system can perform its required operations in the required time. For ML applications involving trained ML model inference, parallel (concurrent) hardware structures can be utilized to perform parallel multiplications usually involving matrix multiplication operations in hardware rather than software. In this paper, fault simulation, embedded instrument test access and built-in self-test (BIST) are considered in relation to the multiply-accumulate (MAC) unit that would be found within a systolic array. A fault simulation was performed on the pre-synthesis MAC unit Verilog HDL design module and used to develop a BIST unit accessible via an IEEE Std 1687 network. The design was prototyped using a Xilinx Artix-7 field programmable gate array (FPGA).