Abstract
We characterize a proposed metastability measurement system in which asynchronous data input and sampling clock frequencies trigger metastability. We develop an equation describing the time interval between data and clock inputs for practical frequencies and show that it takes on discrete values in the absence of jitter and that the presence of jitter perturbs these values. Finally, we present experimental results supporting our characterization.
Original language | English |
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Pages (from-to) | 1032-1040 |
Number of pages | 9 |
Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
Volume | 54 |
Issue number | 5 |
DOIs | |
Publication status | Published - May 2007 |
Keywords
- Circuit reliability
- Digital system testing
- Flip-flops
- Metastability
- Synchronization