Abstract
We characterize the metastability measurement system [8] in which asynchronous data input and sampling clock frequencies trigger metastability. We develop the equation describing the time interval between data and clock inputs for practical frequencies and show that it takes on discrete values in the absence of jitter and that the presence of jitter perturbs these discrete values. Finally, we present experimental results supporting our characterization.
| Original language | English |
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| Title of host publication | ISCAS 2006 |
| Subtitle of host publication | 2006 IEEE International Symposium on Circuits and Systems, Proceedings |
| Pages | 4135-4138 |
| Number of pages | 4 |
| Publication status | Published - 2006 |
| Event | ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: 21 May 2006 → 24 May 2006 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
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| ISSN (Print) | 0271-4310 |
Conference
| Conference | ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems |
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| Country/Territory | Greece |
| City | Kos |
| Period | 21/05/06 → 24/05/06 |