CMOS 260 Mbps read channel with EPRML performance

Thomas Conway; Philip Quinlan; Joe Spalding; Dave Hitchcox; Iuri Mehr; Declan Dalton; Kevin McCall

CMOS 260 Mbps read channel with EPRML performance

Thomas Conway, Philip Quinlan, Joe Spalding, Dave Hitchcox, Iuri Mehr, Declan Dalton, Kevin McCall

Analog Devices, Inc.

Research output: Contribution to conference › Paper › peer-review

Abstract

In this paper, the read channel architecture for a 260 Mbps read channel for magnetic recording applications is presented. The read channel uses a 7 pole 2 zero continuous time filter with a 6 bit flash ADC in the analog front end. The ADC samples are further equalized to the PR4 partial response target with a 5 tap fully asymmetric FIR including LMS adaption. Detection is performed with a PR4 Viterbi detector followed by a postprocessor based on a 16/17(0,6/6) modulation code achieving full EPR4 performance over a range of channel densities. The design is implemented in 0.35u DPTM CMOS and dissipates 1.3 W max at 260 Mbps.

Original language	English
Pages	152-155
Number of pages	4
Publication status	Published - 1998
Externally published	Yes
Event	Proceedings of the 1998 Symposium on VLSI Circuits - Honolulu, HI, USA Duration: 11 Jun 1998 → 13 Jun 1998

Conference

Conference	Proceedings of the 1998 Symposium on VLSI Circuits
City	Honolulu, HI, USA
Period	11/06/98 → 13/06/98

Cite this

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title = "CMOS 260 Mbps read channel with EPRML performance",

abstract = "In this paper, the read channel architecture for a 260 Mbps read channel for magnetic recording applications is presented. The read channel uses a 7 pole 2 zero continuous time filter with a 6 bit flash ADC in the analog front end. The ADC samples are further equalized to the PR4 partial response target with a 5 tap fully asymmetric FIR including LMS adaption. Detection is performed with a PR4 Viterbi detector followed by a postprocessor based on a 16/17(0,6/6) modulation code achieving full EPR4 performance over a range of channel densities. The design is implemented in 0.35u DPTM CMOS and dissipates 1.3 W max at 260 Mbps.",

author = "Thomas Conway and Philip Quinlan and Joe Spalding and Dave Hitchcox and Iuri Mehr and Declan Dalton and Kevin McCall",

year = "1998",

language = "English",

pages = "152--155",

note = "Proceedings of the 1998 Symposium on VLSI Circuits ; Conference date: 11-06-1998 Through 13-06-1998",

}

TY - CONF

T1 - CMOS 260 Mbps read channel with EPRML performance

AU - Conway, Thomas

AU - Quinlan, Philip

AU - Spalding, Joe

AU - Hitchcox, Dave

AU - Mehr, Iuri

AU - Dalton, Declan

AU - McCall, Kevin

PY - 1998

Y1 - 1998

N2 - In this paper, the read channel architecture for a 260 Mbps read channel for magnetic recording applications is presented. The read channel uses a 7 pole 2 zero continuous time filter with a 6 bit flash ADC in the analog front end. The ADC samples are further equalized to the PR4 partial response target with a 5 tap fully asymmetric FIR including LMS adaption. Detection is performed with a PR4 Viterbi detector followed by a postprocessor based on a 16/17(0,6/6) modulation code achieving full EPR4 performance over a range of channel densities. The design is implemented in 0.35u DPTM CMOS and dissipates 1.3 W max at 260 Mbps.

AB - In this paper, the read channel architecture for a 260 Mbps read channel for magnetic recording applications is presented. The read channel uses a 7 pole 2 zero continuous time filter with a 6 bit flash ADC in the analog front end. The ADC samples are further equalized to the PR4 partial response target with a 5 tap fully asymmetric FIR including LMS adaption. Detection is performed with a PR4 Viterbi detector followed by a postprocessor based on a 16/17(0,6/6) modulation code achieving full EPR4 performance over a range of channel densities. The design is implemented in 0.35u DPTM CMOS and dissipates 1.3 W max at 260 Mbps.

UR - http://www.scopus.com/inward/record.url?scp=0031621634&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0031621634

SP - 152

EP - 155

T2 - Proceedings of the 1998 Symposium on VLSI Circuits

Y2 - 11 June 1998 through 13 June 1998

ER -

CMOS 260 Mbps read channel with EPRML performance

Abstract

Conference

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