Developing a Test Strategy for Mathematics of Arrays Computation Cores

Small size, hardware-only, custom data processing cores connected to a host processor are increasingly considered in digital systems design to provide the ability for accelerating data processing operations through hardware acceleration and parallel processing. These can be realized in different forms such as a custom core connected to a host processor on the same die as the processor, as a separate die (e.g., a chiplet) within the same package as the processor or as a separate Integrated Circuit. These require advanced design flows, low-geometry fabrication processes, and suitable test circuit insertion to implement a suitable test strategy. In this paper, the testability of custom hardware cores is considered through test circuit insertion based on the IJTAG standard. The core is to perform data processing operations based on the Mathematics of Arrays and serial communications is based on the Serial Peripheral Interface. This interface is used for both normal operating mode and the IJTAG based test mode. The system design is considered at the pre-synthesis design development stage and identifies architectural considerations for such system designs.