DFT: Scan testing issues and current research

Ivano Indino, Ciaran MacNamee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An inevitable consequence of technology scaling (and the resulting density growth of transistors) in IC design has been the increased power consumption in a chip during functional mode. Technology scaling has been accompanied by a linear reduction of supply voltage for the devices, but the exponential density increase of transistors allowed power density to continue its rapid ascent to levels that created two new obstacles: heat dissipation issues and power supply problems. These issues get magnified during the application of test techniques such as scan testing which is extensively used because it reduces test time and keeps test cost within a reasonable limit. Scan design is currently the most popular structured design for testability (DFT) method used in industry.

Original languageEnglish
Title of host publicationIET Conference Publications
PublisherInstitution of Engineering and Technology
Pages227-232
Number of pages6
EditionCP639
ISBN (Print)9781849199247
DOIs
Publication statusPublished - 2014
Event25th IET Irish Signals and Systems Conference, ISSC 2014 and China-Ireland International Conference on Information and Communications Technologies, CIICT 2014 - Limerick, Ireland
Duration: 26 Jun 201427 Jun 2014

Publication series

NameIET Conference Publications
NumberCP639
Volume2014

Conference

Conference25th IET Irish Signals and Systems Conference, ISSC 2014 and China-Ireland International Conference on Information and Communications Technologies, CIICT 2014
Country/TerritoryIreland
CityLimerick
Period26/06/1427/06/14

Keywords

  • DFT
  • Power-issues
  • Scan testing

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