TY - GEN
T1 - Digital control scheme for robust clock tuning and PWM phase synchronization in digitally controlled multi-POL applications
AU - O'Malley, Eamon
AU - Rinne, Karl
AU - Kelly, Anthony
AU - Almukhtar, Basil
AU - Kelleher, Paul
PY - 2010
Y1 - 2010
N2 - This paper describes a novel clock tuning and subsequent PWM phase synchronization scheme for digitally controlled switching power converters. Its architecture and circuit blocks are presented and explained in detail. The scheme has been implemented in a commercially available digital controller integrated circuit (IC) using a standard CMOS process. Experimental results from a multi point-of-load (POL) application are presented.
AB - This paper describes a novel clock tuning and subsequent PWM phase synchronization scheme for digitally controlled switching power converters. Its architecture and circuit blocks are presented and explained in detail. The scheme has been implemented in a commercially available digital controller integrated circuit (IC) using a standard CMOS process. Experimental results from a multi point-of-load (POL) application are presented.
UR - http://www.scopus.com/inward/record.url?scp=77952136615&partnerID=8YFLogxK
U2 - 10.1109/APEC.2010.5433497
DO - 10.1109/APEC.2010.5433497
M3 - Conference contribution
AN - SCOPUS:77952136615
SN - 9781424447824
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 1922
EP - 1926
BT - APEC 2010 - 25th Annual IEEE Applied Power Electronics Conference and Exposition
T2 - 25th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2010
Y2 - 21 February 2010 through 25 February 2010
ER -