Efficient and high speed FPGA Bump in the wire implementation for data integrity and confidentiality services in the IoT

Data integrity is a term used when referring to the accuracy and reliability of data. It ensures that data is identically maintained during any operation, such as transfer, storage, or retrieval. Any changes to data, for example malicious intention, unpredicted hardware failure or human error would results in failure of data integrity. Cryptographic hash functions are generally used to provide for the verification of data integrity. The Internet of Things (IoT) is a world where billions of objects can sense, share information and communicate over interconnected public or private Internet Protocol (IP) networks. As the adoption of IoT becomes pervasive, the quantity of data that is captured and stored becomes larger. For many IoT applications, hardware implementations of cryptographic hash algorithms will be needed to provide high speed and near real time data integrity checking. ASICs and FPGAs are the two hardware platforms that can be used for these implementations. Currently FPGA is seen as the best leading platform of the modern era in terms of flexibility, reliability and re-configurability. In this chapter an efficient high speed FPGA implementation of the newly selected hash algorithm, SHA-3, is proposed. This high speed implementation can be used with IoT applications to provide near real time data integrity checks. In addition an efficient FPGA based implementation of the Advanced Encryption Standard (AES) is provided. The provision of these FPGA based implementations allows both data integrity and data confidentiality to be provided for high speed IoT applications in addition to enabling low cost Bump In The Wire (BITW) technology to be provided for Internet Protocol Security (IPSec) provision for all IoT applications.