ESD event simulation automation using automatic extraction of the relevant portion of a full chip

Thorsten Weyl, Dave Clarke, Karl Rinne, James A. Power

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An ESD SPICE simulation design analysis flow for a diverse design environment is introduced. Since the complexities of today's integrated circuits often make full chip transient simulations impractical and in many cases even impossible, this flow includes the automatic extraction of the relevant devices for a given ESD stress. An additional challenge is posed by the high number of simulations required for a comprehensive ESD analysis. To obtain timely results and cater for all required stress pin combinations, the simulations are run in parallel in a compute farm environment. For small to medium designs, a complete ESD performance assessment is typically available within several hours.

Original languageEnglish
Title of host publicationProceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009
Pages414-418
Number of pages5
DOIs
Publication statusPublished - 2009
Event10th International Symposium on Quality Electronic Design, ISQED 2009 - San Jose, CA, United States
Duration: 16 Mar 200918 Mar 2009

Publication series

NameProceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

Conference

Conference10th International Symposium on Quality Electronic Design, ISQED 2009
Country/TerritoryUnited States
CitySan Jose, CA
Period16/03/0918/03/09

Keywords

  • CAD tool
  • Circuit simulation
  • Electrostatic discharge
  • Net list analysis
  • Simulation flow

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