@inproceedings{bc9d146c561a4ab58cc88a0c6001df8a,
title = "ESD event simulation automation using automatic extraction of the relevant portion of a full chip",
abstract = "An ESD SPICE simulation design analysis flow for a diverse design environment is introduced. Since the complexities of today's integrated circuits often make full chip transient simulations impractical and in many cases even impossible, this flow includes the automatic extraction of the relevant devices for a given ESD stress. An additional challenge is posed by the high number of simulations required for a comprehensive ESD analysis. To obtain timely results and cater for all required stress pin combinations, the simulations are run in parallel in a compute farm environment. For small to medium designs, a complete ESD performance assessment is typically available within several hours.",
keywords = "CAD tool, Circuit simulation, Electrostatic discharge, Net list analysis, Simulation flow",
author = "Thorsten Weyl and Dave Clarke and Karl Rinne and Power, {James A.}",
year = "2009",
doi = "10.1109/ISQED.2009.4810330",
language = "English",
isbn = "9781424429530",
series = "Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009",
pages = "414--418",
booktitle = "Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009",
note = "10th International Symposium on Quality Electronic Design, ISQED 2009 ; Conference date: 16-03-2009 Through 18-03-2009",
}