Evolving Behavioural Level Sequence Detectors in SystemVerilog Using Grammatical Evolution

Sequential circuits are time-dependent circuits whose output depends not only on their current inputs but also on previous ones. This makes them substantially more complex than combinational circuits, which are stateless and only produce outputs from their current inputs. This paper demonstrates the automatic evolution of some of the most critical and hard-to-evolve electronic sequential circuits, namely, sequence detectors. The circuits are generated at behavioural level using the Hardware Description Language, SystemVerilog. We successfully evolve solutions ranging in complexity from 3 to 5 bits, with and without encapsulation, and 6 bits with encapsulation while using Grammatical Evolution. A uniform distribution of values that a vector of 50 bits can represent was used to generate the random training and test data sets to prevent any bias in the solutions and results. While previous work combined shorter sequence detectors to produce longer ones, for example, combining two 3-bit detectors to form a 6-bit detector, we produce all sequence detectors from scratch without any intermediate stages. The system simply takes instructions and testcases and produces the desired detector; we show that not only does it produce longer-sequence detectors than previous work, but it also does it using fewer computational resources.