FPGA-based digital pulse width modulator with optimized linearity

Martin Scharrer; Mark Halton; Tony Scanlan

doi:10.1109/APEC.2009.4802819

FPGA-based digital pulse width modulator with optimized linearity

Martin Scharrer, Mark Halton, Tony Scanlan

Department of Electronics & Computer Engineering

University of Limerick

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper proposes a new FPGA based architecture for digital pulse width modulators which takes advantage of dedicated digital clock manager (DCM) blocks present in modern FPGAs and applies manual placement techniques to match internal delays for high linearity. The proposed hybrid DPWM uses a synchronous counterbased coarse-resolution block and a DCM based fine-resolution block implementing a synchronous delay line. The design was successfully implemented on a low-cost Xilinx Spartan-3 FPGA with 9-bit resolution with a switching frequency of 1 MHz. Linearity was manually optimized using the presented technique which reduced the integral non-linearity error by 0.5 LSB.

Original language	English
Title of host publication	24th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2009
Pages	1220-1225
Number of pages	6
DOIs	https://doi.org/10.1109/APEC.2009.4802819
Publication status	Published - 2009
Event	24th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2009 - Washington, DC, United States Duration: 15 Feb 2009 → 19 Feb 2009

Publication series

Name	Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Conference

Conference	24th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2009
Country/Territory	United States
City	Washington, DC
Period	15/02/09 → 19/02/09

Access to Document

10.1109/APEC.2009.4802819

Cite this

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title = "FPGA-based digital pulse width modulator with optimized linearity",

abstract = "This paper proposes a new FPGA based architecture for digital pulse width modulators which takes advantage of dedicated digital clock manager (DCM) blocks present in modern FPGAs and applies manual placement techniques to match internal delays for high linearity. The proposed hybrid DPWM uses a synchronous counterbased coarse-resolution block and a DCM based fine-resolution block implementing a synchronous delay line. The design was successfully implemented on a low-cost Xilinx Spartan-3 FPGA with 9-bit resolution with a switching frequency of 1 MHz. Linearity was manually optimized using the presented technique which reduced the integral non-linearity error by 0.5 LSB.",

author = "Martin Scharrer and Mark Halton and Tony Scanlan",

year = "2009",

doi = "10.1109/APEC.2009.4802819",

language = "English",

isbn = "9781424428120",

series = "Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC",

pages = "1220--1225",

booktitle = "24th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2009",

note = "24th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2009 ; Conference date: 15-02-2009 Through 19-02-2009",

}

Scharrer, M, Halton, M & Scanlan, T 2009, FPGA-based digital pulse width modulator with optimized linearity. in 24th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2009., 4802819, Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC, pp. 1220-1225, 24th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2009, Washington, DC, United States, 15/02/09. https://doi.org/10.1109/APEC.2009.4802819

FPGA-based digital pulse width modulator with optimized linearity. / Scharrer, Martin; Halton, Mark ; Scanlan, Tony.
24th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2009. 2009. p. 1220-1225 4802819 (Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Halton, Mark

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AB - This paper proposes a new FPGA based architecture for digital pulse width modulators which takes advantage of dedicated digital clock manager (DCM) blocks present in modern FPGAs and applies manual placement techniques to match internal delays for high linearity. The proposed hybrid DPWM uses a synchronous counterbased coarse-resolution block and a DCM based fine-resolution block implementing a synchronous delay line. The design was successfully implemented on a low-cost Xilinx Spartan-3 FPGA with 9-bit resolution with a switching frequency of 1 MHz. Linearity was manually optimized using the presented technique which reduced the integral non-linearity error by 0.5 LSB.

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ER -

FPGA-based digital pulse width modulator with optimized linearity

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