TY - GEN
T1 - From chip to cooling tower data center modeling
T2 - ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, InterPACK 2011
AU - Breen, Thomas J.
AU - Walsh, Ed J.
AU - Punch, Jeff
AU - Shah, Amip J.
AU - Bash, Cullen E.
AU - Kumari, Niru
AU - Cader, Tahir
PY - 2011
Y1 - 2011
N2 - The power consumption of the chip package is known to vary with operating temperature, independently of the workload processing power. This variation is commonly known as chip leakage power, typically accounting for ∼10% of total chip power consumption. The influence of operating temperature on leakage power consumption is a major concern for the IT industry for design optimization where IT system power densities are steadily increasing and leakage power expected to account for up to ∼50% of chip power in the near future associated with the reducing package size. Much attention has been placed on developing models of the chip leakage power as a function of package temperature, ranging from simple linear models to complex super-linear models. This knowledge is crucial for IT system designers to improve chip level energy efficiency and minimize heat dissipation. However, this work has been focused on the component level with little thought given to the impact of chip leakage power on entire data center efficiency. Studies on data center power consumption quote IT system heat dissipation as a constant value without accounting for the variance of chip power with operating temperature due to leakage power. Previous modeling techniques have also omitted this temperature dependent relationship. In this paper we discuss the need for chip leakage power to be included in the analysis of holistic data center performance. A chip leakage power model is defined and its implementation into an existing multi-scale data center energy model is discussed. Parametric studies are conducted over a range of system and environment operating conditions to evaluate the impact of varying degrees of chip leakage power. Possible strategies for mitigating the impact of leakage power are also illustrated in this study. This work illustrates that when including chip leakage power in the data center model, a compromise exists between increasing operating temperatures to improve cooling infrastructure efficiency and the increase in heat load at higher operating temperatures due to leakage power.
AB - The power consumption of the chip package is known to vary with operating temperature, independently of the workload processing power. This variation is commonly known as chip leakage power, typically accounting for ∼10% of total chip power consumption. The influence of operating temperature on leakage power consumption is a major concern for the IT industry for design optimization where IT system power densities are steadily increasing and leakage power expected to account for up to ∼50% of chip power in the near future associated with the reducing package size. Much attention has been placed on developing models of the chip leakage power as a function of package temperature, ranging from simple linear models to complex super-linear models. This knowledge is crucial for IT system designers to improve chip level energy efficiency and minimize heat dissipation. However, this work has been focused on the component level with little thought given to the impact of chip leakage power on entire data center efficiency. Studies on data center power consumption quote IT system heat dissipation as a constant value without accounting for the variance of chip power with operating temperature due to leakage power. Previous modeling techniques have also omitted this temperature dependent relationship. In this paper we discuss the need for chip leakage power to be included in the analysis of holistic data center performance. A chip leakage power model is defined and its implementation into an existing multi-scale data center energy model is discussed. Parametric studies are conducted over a range of system and environment operating conditions to evaluate the impact of varying degrees of chip leakage power. Possible strategies for mitigating the impact of leakage power are also illustrated in this study. This work illustrates that when including chip leakage power in the data center model, a compromise exists between increasing operating temperatures to improve cooling infrastructure efficiency and the increase in heat load at higher operating temperatures due to leakage power.
UR - http://www.scopus.com/inward/record.url?scp=84860343593&partnerID=8YFLogxK
U2 - 10.1115/IPACK2011-52030
DO - 10.1115/IPACK2011-52030
M3 - Conference contribution
AN - SCOPUS:84860343593
SN - 9780791844618
T3 - ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, InterPACK 2011
SP - 433
EP - 442
BT - ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, InterPACK 2011
Y2 - 6 July 2011 through 8 July 2011
ER -