Grammatical Evolution of Synthesizable Finite State Machine-Based Behavioural Level Hardware Description Language Codes

The importance of designing efficient and accurate digital circuits has grown due to the widespread use of wearable, ready-made, and custom electronic products. These digital circuits are typically sequential and designed using synthesizable Hardware Description Languages (HDLs) that can be translated into hardware. A large part of this exercise comprises designing synthesizable HDLs for sequential circuits, which are challenging to design and test, thus requiring much time for the engineers to construct them. This paper proposes using Grammatical Evolution (GE) to evolve the synthesizable HDL codes for sequential circuits on the behavioural or algorithmic level in SystemVerilog. The codes evolved in this work are of JK-Flip Flop (JK-FF), 3-bit UpDown Counter (UDC), and 8-Floor Elevator (8FE), all from the perspective of Finite State Machines (FSMs). Circuits such as 3-bit UDC and JK-FF are the basic blocks in many circuits in the industry, while 8FE is a real-life example mimicking 3-bit UDC but with a few practical exceptions. All circuits are evolved using two types of grammars. The G1 Type Grammar evolves parts of the code, while the more powerful and generic G2 Type Grammar evolves the full HDL codes for these sequential circuits. The GE-based evolution of these synthesizable design codes using both types of grammar achieves a success rate of over 86% for all circuits. Moreover, all the solution circuits evolved with the best achieved success score under the respective hyperparameter settings for G1 and G2 Type Grammar are synthesised, and their synthesis reports are compared against the synthesis reports of Gold (human-designed) circuits. The synthesis is performed using Cadence Genus at Generic Process Design Kit (GPDK) 45, 90, and 180 nm technology libraries. The synthesis results show that machine-generated designs often perform as well as or better than human-designed circuits.