High order dynamic element matching for multibit delta sigma A/D & D/A converters

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Abstract

This paper presents a reduced area high order Dynamic Element Matching (DEM) scheme for use with multi-bit Delta Sigma data converters. The design leverages the increased digital signal processing afforded by low geometry CMOS processes to both improve performance and reduce analog circuit area. Within the converter, dual vector feedback DEMs are combined using a noise shaped splitter, this reduces logic area while providing 2nd order mismatch error shaping.

Original languageEnglish
Title of host publicationIET Conference Publications
PublisherInstitution of Engineering and Technology
Pages418-423
Number of pages6
EditionCP639
ISBN (Print)9781849199247
DOIs
Publication statusPublished - 2014
Event25th IET Irish Signals and Systems Conference, ISSC 2014 and China-Ireland International Conference on Information and Communications Technologies, CIICT 2014 - Limerick, Ireland
Duration: 26 Jun 201427 Jun 2014

Publication series

NameIET Conference Publications
NumberCP639
Volume2014

Conference

Conference25th IET Irish Signals and Systems Conference, ISSC 2014 and China-Ireland International Conference on Information and Communications Technologies, CIICT 2014
Country/TerritoryIreland
CityLimerick
Period26/06/1427/06/14

Keywords

  • ADC
  • DAC
  • Delta-Sigma
  • DEM

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