High Order Mismatch Shaping for Low Oversampling Rates

Vincent O'Brien; Brendan Mullane

doi:10.1109/TCSII.2019.2904180

High Order Mismatch Shaping for Low Oversampling Rates

Vincent O'Brien, Brendan Mullane

Department of Electronics & Computer Engineering

South East Technological University

Research output: Contribution to journal › Article › peer-review

Abstract

Delta Sigma data converters employing high order dynamic element matching (DEM) allow for accurate signal conversion in the presence of DAC mismatch. However, at low oversampling rates, current high order DEM decoders provide little or no improvement in error suppression over lower order designs. In addition, the logic requirement of the DEM decoder increases significantly with each additional DAC bit. This brief presents a high order DEM decoder that improves mismatch shaping performance at low to medium oversampling rates by up to 15 dB, while employing methods to reduce the area overhead of the vector quantizer in the design.

Original language	English
Article number	8664116
Pages (from-to)	42-46
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	67
Issue number	1
DOIs	https://doi.org/10.1109/TCSII.2019.2904180
Publication status	Published - Jan 2020

Keywords

ADC
DAC
decoder
delta sigma (Δ Σ)
DEM
dynamic element matching
element selection logic
mismatch shaping
oversampling

Access to Document

10.1109/TCSII.2019.2904180

Cite this

@article{77b671371f6041ce923b2c7a82cb65cf,

title = "High Order Mismatch Shaping for Low Oversampling Rates",

abstract = "Delta Sigma data converters employing high order dynamic element matching (DEM) allow for accurate signal conversion in the presence of DAC mismatch. However, at low oversampling rates, current high order DEM decoders provide little or no improvement in error suppression over lower order designs. In addition, the logic requirement of the DEM decoder increases significantly with each additional DAC bit. This brief presents a high order DEM decoder that improves mismatch shaping performance at low to medium oversampling rates by up to 15 dB, while employing methods to reduce the area overhead of the vector quantizer in the design.",

keywords = "ADC, DAC, decoder, delta sigma (Δ Σ), DEM, dynamic element matching, element selection logic, mismatch shaping, oversampling",

author = "Vincent O'Brien and Brendan Mullane",

note = "Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2020",

month = jan,

doi = "10.1109/TCSII.2019.2904180",

language = "English",

volume = "67",

pages = "42--46",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

number = "1",

}

TY - JOUR

T1 - High Order Mismatch Shaping for Low Oversampling Rates

AU - O'Brien, Vincent

AU - Mullane, Brendan

PY - 2020/1

Y1 - 2020/1

N2 - Delta Sigma data converters employing high order dynamic element matching (DEM) allow for accurate signal conversion in the presence of DAC mismatch. However, at low oversampling rates, current high order DEM decoders provide little or no improvement in error suppression over lower order designs. In addition, the logic requirement of the DEM decoder increases significantly with each additional DAC bit. This brief presents a high order DEM decoder that improves mismatch shaping performance at low to medium oversampling rates by up to 15 dB, while employing methods to reduce the area overhead of the vector quantizer in the design.

AB - Delta Sigma data converters employing high order dynamic element matching (DEM) allow for accurate signal conversion in the presence of DAC mismatch. However, at low oversampling rates, current high order DEM decoders provide little or no improvement in error suppression over lower order designs. In addition, the logic requirement of the DEM decoder increases significantly with each additional DAC bit. This brief presents a high order DEM decoder that improves mismatch shaping performance at low to medium oversampling rates by up to 15 dB, while employing methods to reduce the area overhead of the vector quantizer in the design.

KW - ADC

KW - DAC

KW - decoder

KW - delta sigma (Δ Σ)

KW - DEM

KW - dynamic element matching

KW - element selection logic

KW - mismatch shaping

KW - oversampling

UR - http://www.scopus.com/inward/record.url?scp=85077370428&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2019.2904180

DO - 10.1109/TCSII.2019.2904180

M3 - Article

AN - SCOPUS:85077370428

SN - 1549-7747

VL - 67

SP - 42

EP - 46

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 1

M1 - 8664116

ER -

High Order Mismatch Shaping for Low Oversampling Rates

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this