IEEE 1500 core wrapper optimization techniques and implementation

Brendan Mullane; Michael Higgins; Ciaran MacNamee

doi:10.1109/TEST.2008.4700629

IEEE 1500 core wrapper optimization techniques and implementation

Brendan Mullane
, Michael Higgins
, Ciaran MacNamee

Department of Electronics & Computer Engineering

University of Limerick

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

IEEE 1500 core wrappers supporting a hybrid scan mode provide for lower test times with minimal wiring and logic overheads. Wrapper logic and vector formats that are easily integrated with modern IC/FPGA design flows are demonstrated.

Original language	English
Title of host publication	Proceedings - International Test Conference 2008, ITC 2008
DOIs	https://doi.org/10.1109/TEST.2008.4700629
Publication status	Published - 2008
Event	International Test Conference 2008, ITC 2008 - Santa Clara, CA, United States Duration: 28 Oct 2008 → 30 Oct 2008

Publication series

Name	Proceedings - International Test Conference
ISSN (Print)	1089-3539

Conference

Conference	International Test Conference 2008, ITC 2008
Country/Territory	United States
City	Santa Clara, CA
Period	28/10/08 → 30/10/08

Access to Document

10.1109/TEST.2008.4700629

Cite this

@inproceedings{7f16387664ff4f25a4c6349f31177bc3,

title = "IEEE 1500 core wrapper optimization techniques and implementation",

abstract = "IEEE 1500 core wrappers supporting a hybrid scan mode provide for lower test times with minimal wiring and logic overheads. Wrapper logic and vector formats that are easily integrated with modern IC/FPGA design flows are demonstrated.",

author = "Brendan Mullane and Michael Higgins and Ciaran MacNamee",

year = "2008",

doi = "10.1109/TEST.2008.4700629",

language = "English",

isbn = "9781424424030",

series = "Proceedings - International Test Conference",

booktitle = "Proceedings - International Test Conference 2008, ITC 2008",

note = "International Test Conference 2008, ITC 2008 ; Conference date: 28-10-2008 Through 30-10-2008",

}

TY - GEN

T1 - IEEE 1500 core wrapper optimization techniques and implementation

AU - Mullane, Brendan

AU - Higgins, Michael

AU - MacNamee, Ciaran

PY - 2008

Y1 - 2008

N2 - IEEE 1500 core wrappers supporting a hybrid scan mode provide for lower test times with minimal wiring and logic overheads. Wrapper logic and vector formats that are easily integrated with modern IC/FPGA design flows are demonstrated.

AB - IEEE 1500 core wrappers supporting a hybrid scan mode provide for lower test times with minimal wiring and logic overheads. Wrapper logic and vector formats that are easily integrated with modern IC/FPGA design flows are demonstrated.

UR - https://www.scopus.com/pages/publications/67249145929

U2 - 10.1109/TEST.2008.4700629

DO - 10.1109/TEST.2008.4700629

M3 - Conference contribution

AN - SCOPUS:67249145929

SN - 9781424424030

T3 - Proceedings - International Test Conference

BT - Proceedings - International Test Conference 2008, ITC 2008

T2 - International Test Conference 2008, ITC 2008

Y2 - 28 October 2008 through 30 October 2008

ER -

IEEE 1500 core wrapper optimization techniques and implementation

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this