Implementation of high speed Viterbi detectors

The parallel architecture of the add compare select (ACS) unit reorders the required calculations by doubling the number of path metric registers while allowing the speed of operation to be increased by allowing the branch metric adders to be completed in parallel with the comparison rather than in series. When this is combined with a latch based metric storage element, a significant improvement in speed compared to the normal ACS architecture is achieved without the significant area penalty of the radix 4 architecture. The achievable performance was determined by a synthesized EPR4 detector using the parallel and conventional architectures.