Lifting scheme discrete wavelet transform using vertical and crosswise multipliers

In this paper, a power/area efficient multiplier for field programmable gate array (FPGA) logic is proposed using fast arithmetic techniques. An optimised multiplier based on Vedic mathematics is proposed to improve the power dissipation compared with other common parallel multipliers (e.g. Booth, Carry Save, etc). This paper implements a lifting step function used in second generation discrete wavelet transform (DWT). Multiplication is the main arithmetic operation used in the lifting scheme and the proposed method reduces the total power requirements. An arithmetic block (AB) using an optimised vertical and crosswise (VC) multipliers structure, implements the lifting step function. The lifting step and multiplier was designed and synthesized using Altera Quartas II on a Stratix II EP2S15F484C3 device. The results show the total power dissipation of the lifting step with carry-save (CS) and the carry-ripple (CR) array multipliers were 6.92% and 28.69% higher than its vertical and crosswise implementation. The lifting step based on CS-VC compared to the Booth-1 had 80.53% lower total power dissipation and 73.19% relative to Booth-3 based multipliers.