Live demostration: 'Ripple sort' algorithm, circuit implementation and verification using VHDL synthesisable testbench verification technique

Ching Y. Man; Elfed Lewis; Brian Moss

doi:10.1109/ICSENS.2015.7370293

Live demostration: 'Ripple sort' algorithm, circuit implementation and verification using VHDL synthesisable testbench verification technique

Ching Y. Man, Elfed Lewis, Brian Moss

Department of Electronics & Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This demonstration centered around the, design, simulation and verification of the 'Ripple Sort Algorithm and circuit implementation' [1] using VHDL synthesizable testbench verification techniques. The purpose of this demonstration is to show; the advantages and benefits for using synthesizable testbench verification techniques by means of inexpensive off-the-shelf tools. How an ASIC/FPGA design can be automated, checked for bugs and rapidly verified.

Original language	English
Title of host publication	2015 IEEE SENSORS - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479982028
DOIs	https://doi.org/10.1109/ICSENS.2015.7370293
Publication status	Published - 31 Dec 2015
Event	14th IEEE SENSORS - Busan, Korea, Republic of Duration: 1 Nov 2015 → 4 Nov 2015

Publication series

Name	2015 IEEE SENSORS - Proceedings

Conference

Conference	14th IEEE SENSORS
Country/Territory	Korea, Republic of
City	Busan
Period	1/11/15 → 4/11/15

Access to Document

10.1109/ICSENS.2015.7370293

Cite this

Man, C. Y., Lewis, E., & Moss, B. (2015). Live demostration: 'Ripple sort' algorithm, circuit implementation and verification using VHDL synthesisable testbench verification technique. In 2015 IEEE SENSORS - Proceedings Article 7370293 (2015 IEEE SENSORS - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSENS.2015.7370293

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title = "Live demostration: 'Ripple sort' algorithm, circuit implementation and verification using VHDL synthesisable testbench verification technique",

abstract = "This demonstration centered around the, design, simulation and verification of the 'Ripple Sort Algorithm and circuit implementation' [1] using VHDL synthesizable testbench verification techniques. The purpose of this demonstration is to show; the advantages and benefits for using synthesizable testbench verification techniques by means of inexpensive off-the-shelf tools. How an ASIC/FPGA design can be automated, checked for bugs and rapidly verified.",

author = "Man, {Ching Y.} and Elfed Lewis and Brian Moss",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 14th IEEE SENSORS ; Conference date: 01-11-2015 Through 04-11-2015",

year = "2015",

month = dec,

day = "31",

doi = "10.1109/ICSENS.2015.7370293",

language = "English",

series = "2015 IEEE SENSORS - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Man, CY, Lewis, E & Moss, B 2015, Live demostration: 'Ripple sort' algorithm, circuit implementation and verification using VHDL synthesisable testbench verification technique. in 2015 IEEE SENSORS - Proceedings., 7370293, 2015 IEEE SENSORS - Proceedings, Institute of Electrical and Electronics Engineers Inc., 14th IEEE SENSORS, Busan, Korea, Republic of, 1/11/15. https://doi.org/10.1109/ICSENS.2015.7370293

Live demostration: 'Ripple sort' algorithm, circuit implementation and verification using VHDL synthesisable testbench verification technique. / Man, Ching Y.; Lewis, Elfed; Moss, Brian.
2015 IEEE SENSORS - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. 7370293 (2015 IEEE SENSORS - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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PY - 2015/12/31

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N2 - This demonstration centered around the, design, simulation and verification of the 'Ripple Sort Algorithm and circuit implementation' [1] using VHDL synthesizable testbench verification techniques. The purpose of this demonstration is to show; the advantages and benefits for using synthesizable testbench verification techniques by means of inexpensive off-the-shelf tools. How an ASIC/FPGA design can be automated, checked for bugs and rapidly verified.

AB - This demonstration centered around the, design, simulation and verification of the 'Ripple Sort Algorithm and circuit implementation' [1] using VHDL synthesizable testbench verification techniques. The purpose of this demonstration is to show; the advantages and benefits for using synthesizable testbench verification techniques by means of inexpensive off-the-shelf tools. How an ASIC/FPGA design can be automated, checked for bugs and rapidly verified.

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Live demostration: 'Ripple sort' algorithm, circuit implementation and verification using VHDL synthesisable testbench verification technique

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