Logically Optimized Smallest FPGA Architecture for SHA- 3 Core

This work proposes a logically optimized smallest arithmetic architecture for the new Secure Hash Algorithm-3 (SHA-3) core using the Look-Up-Table (LUT) resources of FPGA. In this work a novel technique for compact implementation of SHA-3 core is discussed. The Logical operations of the SHA-3 core are optimized using Boolean equations and the result is saved in LUT_6 primitives available in modern Xilinx FPGAs. The proposed architecture consists of 64 LUT_6 primitives and these LUTs are used throughout the compression function operation. Work is still in progress on control circuitry in which we are trying to access internal resources of FPGA. So results of only Core implantation are discussed now and will be updated after designing of control circuitry.