Machine Learning Framework for Automated Transistor-Level Analogue and Digital Circuit Synthesis

Transistor-level Integrated Circuit (IC) design is fundamental to modern electronics, yet it remains one of the most expertise-intensive and time-consuming stages of chip development. As circuit complexity continues to rise, the need to automate this low-level design process has become critical to sustaining innovation and productivity across the semiconductor industry. This study presents a fully automated methodology for transistor-level IC design using a novel framework that integrates Grammatical Evolution (GE) with Cadence SKILL code. Beyond automation, the framework explicitly examines how symmetry and asymmetry shape the evolutionary search space and resulting circuit structures. To address the time-consuming and expertise-intensive nature of conventional integrated circuit design, the framework automates the synthesis of both digital and analogue circuits without requiring prior domain knowledge. A specialised attribute grammar (AG) evolves circuit topology and sizing, with performance assessed by a multi-objective fitness function. Symmetry is analysed at three levels: (i) domain-level structural dualities (e.g., NAND/NOR mirror topologies and PMOS/NMOS exchanges), (ii) objective-level symmetries created by logic threshold settings, and (iii) representational symmetries managed through grammatical constraints that preserve valid connectivity while avoiding redundant isomorphs. Validation was carried out on universal logic gates (NAND and NOR) at multiple logic thresholds, as well as on a temperature sensor. Under stricter thresholds, the evolved logic gates display emergent duality, converging to mirror-image transistor configurations; relaxed thresholds increase symmetric plateaus and slow convergence. The evolved logic gates achieve superior performance over conventional Complementary Metal–Oxide–Semiconductor (CMOS), Transmission Gate Logic (TGL), and Gate Diffusion Input (GDI) implementations, demonstrating lower power consumption, a reduced Power–Delay Product (PDP), and fewer transistors. Similarly, the evolved temperature sensor exhibits improved sensitivity, reduced power, and Integral Nonlinearity (INL), and a smaller area compared to the conventional Proportional to Absolute Temperature (PTAT) or “gold” circuit, without requiring resistors. The analogue design further demonstrates beneficial asymmetry in device roles, breaking canonical structures to achieve higher performance. Across all case studies, the evolved designs matched or outperformed their manually designed counterparts, demonstrating that this GE-based approach provides a scalable and effective path toward fully automated, symmetry-aware integrated circuit synthesis.