TY - JOUR
T1 - Monitoring embedded software timing properties with an SoC-resident monitor
AU - Heffernan, D.
AU - Shaheen, S.
AU - Watterson, C.
PY - 2009
Y1 - 2009
N2 - Many safety-critical software applications are hard real-time systems. They have stringent timing requirements that have to be adhered to. Functional timing requirements need to interact properly with performance timing requirements. A novel runtime monitor that can check for proper timing behaviour of software, in the actual implementation environment, is presented. The monitor can be synthesised from the software's timing requirements specification and instantiated in the programmable digital logic of a system on chip (SoC)-based device. Since the monitor is synthesised from the program's requirements, new monitors can be automatically generated for new programs. Since the SoC-based monitor is deeply embedded, it can operate at the full processor speed and will have access to the internal registers of the processing system. A low gate count, non-invasive monitor is achievable. A case study example, based on a design for an electronic automotive gear controller system, is presented. The study shows that the monitor is capable of detecting program timing violations, in the implementation environment, even though the software design had been properly verified against stated requirements. The monitor scheme can be used as a supplementary test solution or the monitor can be built into a product for lifetime monitoring of timing behaviour, so as to enhance the product's reliability.
AB - Many safety-critical software applications are hard real-time systems. They have stringent timing requirements that have to be adhered to. Functional timing requirements need to interact properly with performance timing requirements. A novel runtime monitor that can check for proper timing behaviour of software, in the actual implementation environment, is presented. The monitor can be synthesised from the software's timing requirements specification and instantiated in the programmable digital logic of a system on chip (SoC)-based device. Since the monitor is synthesised from the program's requirements, new monitors can be automatically generated for new programs. Since the SoC-based monitor is deeply embedded, it can operate at the full processor speed and will have access to the internal registers of the processing system. A low gate count, non-invasive monitor is achievable. A case study example, based on a design for an electronic automotive gear controller system, is presented. The study shows that the monitor is capable of detecting program timing violations, in the implementation environment, even though the software design had been properly verified against stated requirements. The monitor scheme can be used as a supplementary test solution or the monitor can be built into a product for lifetime monitoring of timing behaviour, so as to enhance the product's reliability.
UR - http://www.scopus.com/inward/record.url?scp=64549136734&partnerID=8YFLogxK
U2 - 10.1049/iet-sen.2008.0040
DO - 10.1049/iet-sen.2008.0040
M3 - Article
AN - SCOPUS:64549136734
SN - 1751-8806
VL - 3
SP - 140
EP - 153
JO - IET Software
JF - IET Software
IS - 2
ER -