Novel arithmetic architecture for high performance implementation of SHA-3 finalist Keccak on FPGA platforms

Kashif Latif; M. Muzaffar Rao; Athar Mahboob; Arshad Aziz

doi:10.1007/978-3-642-28365-9_34

Novel arithmetic architecture for high performance implementation of SHA-3 finalist Keccak on FPGA platforms

Kashif Latif, M. Muzaffar Rao, Athar Mahboob, Arshad Aziz

National University of Sciences and Technology Pakistan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

We propose high speed architecture for Keccak using Look-Up Table (LUT) resources on FPGAs, to minimize area of Keccak data path and to reduce critical path lengths. This approach allows us to design Keccak data path with minimum resources and higher clock frequencies. We show our results in the form of chip area consumption, throughput and throughput per area. At this time, the design presented in this work is the highest in terms of throughput for any of SHA-3 candidates, achieving a figure of 13.67Gbps for Keccak-256 on Virtex 6. This can enable line rate operation for hashing on 10Gbps network interfaces.

Original language	English
Title of host publication	Reconfigurable Computing
Subtitle of host publication	Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings
Pages	372-378
Number of pages	7
DOIs	https://doi.org/10.1007/978-3-642-28365-9_34
Publication status	Published - 2012
Externally published	Yes
Event	8th International Symposium on Applied Reconfigurable Computing, ARC 2012 - Hong Kong, China Duration: 19 Mar 2012 → 23 Mar 2012

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	7199 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	8th International Symposium on Applied Reconfigurable Computing, ARC 2012
Country/Territory	China
City	Hong Kong
Period	19/03/12 → 23/03/12

Keywords

Cryptographic Hash Functions
FPGA
High Speed Encryption Hardware
Keccak
Reconfigurable Computing
SHA-3

Access to Document

10.1007/978-3-642-28365-9_34

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Latif, K., Rao, M. M., Mahboob, A., & Aziz, A. (2012). Novel arithmetic architecture for high performance implementation of SHA-3 finalist Keccak on FPGA platforms. In Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings (pp. 372-378). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 7199 LNCS). https://doi.org/10.1007/978-3-642-28365-9_34

Latif, Kashif ; Rao, M. Muzaffar ; Mahboob, Athar et al. / Novel arithmetic architecture for high performance implementation of SHA-3 finalist Keccak on FPGA platforms. Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings. 2012. pp. 372-378 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{6a50adccd60145b7a237c6ffe507a527,

title = "Novel arithmetic architecture for high performance implementation of SHA-3 finalist Keccak on FPGA platforms",

abstract = "We propose high speed architecture for Keccak using Look-Up Table (LUT) resources on FPGAs, to minimize area of Keccak data path and to reduce critical path lengths. This approach allows us to design Keccak data path with minimum resources and higher clock frequencies. We show our results in the form of chip area consumption, throughput and throughput per area. At this time, the design presented in this work is the highest in terms of throughput for any of SHA-3 candidates, achieving a figure of 13.67Gbps for Keccak-256 on Virtex 6. This can enable line rate operation for hashing on 10Gbps network interfaces.",

keywords = "Cryptographic Hash Functions, FPGA, High Speed Encryption Hardware, Keccak, Reconfigurable Computing, SHA-3",

author = "Kashif Latif and Rao, {M. Muzaffar} and Athar Mahboob and Arshad Aziz",

year = "2012",

doi = "10.1007/978-3-642-28365-9_34",

language = "English",

isbn = "9783642283642",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

pages = "372--378",

booktitle = "Reconfigurable Computing",

note = "8th International Symposium on Applied Reconfigurable Computing, ARC 2012 ; Conference date: 19-03-2012 Through 23-03-2012",

}

Latif, K, Rao, MM, Mahboob, A & Aziz, A 2012, Novel arithmetic architecture for high performance implementation of SHA-3 finalist Keccak on FPGA platforms. in Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 7199 LNCS, pp. 372-378, 8th International Symposium on Applied Reconfigurable Computing, ARC 2012, Hong Kong, China, 19/03/12. https://doi.org/10.1007/978-3-642-28365-9_34

Novel arithmetic architecture for high performance implementation of SHA-3 finalist Keccak on FPGA platforms. / Latif, Kashif; Rao, M. Muzaffar; Mahboob, Athar et al.
Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings. 2012. p. 372-378 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 7199 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Novel arithmetic architecture for high performance implementation of SHA-3 finalist Keccak on FPGA platforms

AU - Latif, Kashif

AU - Rao, M. Muzaffar

AU - Mahboob, Athar

AU - Aziz, Arshad

PY - 2012

Y1 - 2012

N2 - We propose high speed architecture for Keccak using Look-Up Table (LUT) resources on FPGAs, to minimize area of Keccak data path and to reduce critical path lengths. This approach allows us to design Keccak data path with minimum resources and higher clock frequencies. We show our results in the form of chip area consumption, throughput and throughput per area. At this time, the design presented in this work is the highest in terms of throughput for any of SHA-3 candidates, achieving a figure of 13.67Gbps for Keccak-256 on Virtex 6. This can enable line rate operation for hashing on 10Gbps network interfaces.

AB - We propose high speed architecture for Keccak using Look-Up Table (LUT) resources on FPGAs, to minimize area of Keccak data path and to reduce critical path lengths. This approach allows us to design Keccak data path with minimum resources and higher clock frequencies. We show our results in the form of chip area consumption, throughput and throughput per area. At this time, the design presented in this work is the highest in terms of throughput for any of SHA-3 candidates, achieving a figure of 13.67Gbps for Keccak-256 on Virtex 6. This can enable line rate operation for hashing on 10Gbps network interfaces.

KW - Cryptographic Hash Functions

KW - FPGA

KW - High Speed Encryption Hardware

KW - Keccak

KW - Reconfigurable Computing

KW - SHA-3

UR - http://www.scopus.com/inward/record.url?scp=84859455513&partnerID=8YFLogxK

U2 - 10.1007/978-3-642-28365-9_34

DO - 10.1007/978-3-642-28365-9_34

M3 - Conference contribution

AN - SCOPUS:84859455513

SN - 9783642283642

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 372

EP - 378

BT - Reconfigurable Computing

T2 - 8th International Symposium on Applied Reconfigurable Computing, ARC 2012

Y2 - 19 March 2012 through 23 March 2012

ER -

Latif K, Rao MM, Mahboob A, Aziz A. Novel arithmetic architecture for high performance implementation of SHA-3 finalist Keccak on FPGA platforms. In Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings. 2012. p. 372-378. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-642-28365-9_34

Novel arithmetic architecture for high performance implementation of SHA-3 finalist Keccak on FPGA platforms

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