TY - GEN
T1 - On-chip instrumentation for runtime verification in deeply embedded processors
AU - Macnamee, Ciaran
AU - Heffernan, Donal
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/10/27
Y1 - 2015/10/27
N2 - In the field of safety-critical applications, the industry has seen a dramatic increase in system integration and complexity for on-chip solutions, and this provides new challenges in gaining deep testability access within such products. IC developers have responded to this challenge by creating sophisticated on-chip trace/test/debug modules to facilitate real-time access to application programs' features in deeply embedded pipeline and cache based architectures for embedded-core-based chips. However, the emerging safety requirements for complex systems demand more stringent solutions for confirming confidence in systems and this leads to a requirement for the formal verification of some key system properties. In this paper the authors propose that the existing architectures for on-chip trace/test/debug modules can be extended to support runtime verification monitoring, working towards the formal verification of system properties of interest. A real benefit in the proposed solution is the provision of a lifecycle use for the on-chip debug logic, thus offering an improved return-on-investment prospect by justifying the resident logic with the benefit gained by lifelong runtime verification features.
AB - In the field of safety-critical applications, the industry has seen a dramatic increase in system integration and complexity for on-chip solutions, and this provides new challenges in gaining deep testability access within such products. IC developers have responded to this challenge by creating sophisticated on-chip trace/test/debug modules to facilitate real-time access to application programs' features in deeply embedded pipeline and cache based architectures for embedded-core-based chips. However, the emerging safety requirements for complex systems demand more stringent solutions for confirming confidence in systems and this leads to a requirement for the formal verification of some key system properties. In this paper the authors propose that the existing architectures for on-chip trace/test/debug modules can be extended to support runtime verification monitoring, working towards the formal verification of system properties of interest. A real benefit in the proposed solution is the provision of a lifecycle use for the on-chip debug logic, thus offering an improved return-on-investment prospect by justifying the resident logic with the benefit gained by lifelong runtime verification features.
KW - Embedded processor
KW - Monitors
KW - On-chip debug
KW - Runtime verification
KW - Safety critical
UR - http://www.scopus.com/inward/record.url?scp=84956968453&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2015.38
DO - 10.1109/ISVLSI.2015.38
M3 - Conference contribution
AN - SCOPUS:84956968453
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 374
EP - 379
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015
PB - IEEE Computer Society
T2 - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015
Y2 - 8 July 2015 through 10 July 2015
ER -