TY - GEN
T1 - Pole-zero estimation and analysis of op-amp design with negative Miller compensation
AU - Zaidi, Muhaned
AU - Grout, Ian
AU - A'Ain, Abu Khari
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/5/31
Y1 - 2017/5/31
N2 - In this paper, pole-zero estimation, analysis and simplification of the transfer function for a two-stage operational amplifier (op-amp) is presented. The circuit design considered is a folded cascode complementary metal oxide semiconductor (CMOS) op-amp incorporating both Miller and negative Miller frequency compensation. The design was created using a 0.35 μm CMOS fabrication process and analyzed for DC gain, unity gain frequency, gain margin, phase margin and open-loop pole and zero locations. Cadence Virtuoso was used for design entry and the Spectre simulator used for circuit level simulation studies. The extracted poles and zeros were used to create the circuit transfer function which was then analyzed using MATLAB. This allowed the transfer function to be simplified by reducing the numbers of poles and zeros for comparison with the frequency response of the original circuit. Finally, a Verilog-A model was created and compared to the original circuit and the MATLAB simulation study results.
AB - In this paper, pole-zero estimation, analysis and simplification of the transfer function for a two-stage operational amplifier (op-amp) is presented. The circuit design considered is a folded cascode complementary metal oxide semiconductor (CMOS) op-amp incorporating both Miller and negative Miller frequency compensation. The design was created using a 0.35 μm CMOS fabrication process and analyzed for DC gain, unity gain frequency, gain margin, phase margin and open-loop pole and zero locations. Cadence Virtuoso was used for design entry and the Spectre simulator used for circuit level simulation studies. The extracted poles and zeros were used to create the circuit transfer function which was then analyzed using MATLAB. This allowed the transfer function to be simplified by reducing the numbers of poles and zeros for comparison with the frequency response of the original circuit. Finally, a Verilog-A model was created and compared to the original circuit and the MATLAB simulation study results.
KW - Miller effect
KW - Operational amplifier
KW - poles and zeros
KW - transfer function
UR - http://www.scopus.com/inward/record.url?scp=85025704671&partnerID=8YFLogxK
U2 - 10.1109/MOCAST.2017.7937617
DO - 10.1109/MOCAST.2017.7937617
M3 - Conference contribution
AN - SCOPUS:85025704671
T3 - 2017 6th International Conference on Modern Circuits and Systems Technologies, MOCAST 2017
BT - 2017 6th International Conference on Modern Circuits and Systems Technologies, MOCAST 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th International Conference on Modern Circuits and Systems Technologies, MOCAST 2017
Y2 - 4 May 2017 through 6 May 2017
ER -