Pulse-Frequency Modulation Signal Generation for Programmable Logic Using Python and VHDL

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Abstract

In this paper, the design and development of a pulse-frequency modulation (PFM) signal generator circuit toolbox targeting the programmable logic device (PLD) is presented. PFM is signal encoding scheme that realizes an analog signal level as a digital bit-stream where the bit-stream frequency is proportional to the analog signal level. It is analogous to pulsewidth modulation (PWM). A Python script is run which sets-up a project and the analog signal to encode into PFM. The user can then generate a PFM signal generator circuit description in VHDL for implementation within a field programmable gate array (FPGA) or complex programmable logic device (CPLD). In this paper, the Xilinx Cool runner-II CPLD is chosen as the target device into which the VHDL circuit description can be synthesized and configured into the CPLD. In addition, a MATLAB script is generated to allow for analysis in MATLAB and a SPICE netlist is generated for analog circuit simulation.

Original languageEnglish
Title of host publicationiEECON 2018 - 6th International Electrical Engineering Congress
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538623176
DOIs
Publication statusPublished - 2 Jul 2018
Event6th International Electrical Engineering Congress, iEECON 2018 - Krabi, Thailand
Duration: 7 Mar 20189 Mar 2018

Publication series

NameiEECON 2018 - 6th International Electrical Engineering Congress

Conference

Conference6th International Electrical Engineering Congress, iEECON 2018
Country/TerritoryThailand
CityKrabi
Period7/03/189/03/18

Keywords

  • PLD
  • pulse-frequency modulation
  • Python
  • VHDL

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