TY - GEN
T1 - Pulse-Frequency Modulation Signal Generation for Programmable Logic Using Python and VHDL
AU - Grout, Ian
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/7/2
Y1 - 2018/7/2
N2 - In this paper, the design and development of a pulse-frequency modulation (PFM) signal generator circuit toolbox targeting the programmable logic device (PLD) is presented. PFM is signal encoding scheme that realizes an analog signal level as a digital bit-stream where the bit-stream frequency is proportional to the analog signal level. It is analogous to pulsewidth modulation (PWM). A Python script is run which sets-up a project and the analog signal to encode into PFM. The user can then generate a PFM signal generator circuit description in VHDL for implementation within a field programmable gate array (FPGA) or complex programmable logic device (CPLD). In this paper, the Xilinx Cool runner-II CPLD is chosen as the target device into which the VHDL circuit description can be synthesized and configured into the CPLD. In addition, a MATLAB script is generated to allow for analysis in MATLAB and a SPICE netlist is generated for analog circuit simulation.
AB - In this paper, the design and development of a pulse-frequency modulation (PFM) signal generator circuit toolbox targeting the programmable logic device (PLD) is presented. PFM is signal encoding scheme that realizes an analog signal level as a digital bit-stream where the bit-stream frequency is proportional to the analog signal level. It is analogous to pulsewidth modulation (PWM). A Python script is run which sets-up a project and the analog signal to encode into PFM. The user can then generate a PFM signal generator circuit description in VHDL for implementation within a field programmable gate array (FPGA) or complex programmable logic device (CPLD). In this paper, the Xilinx Cool runner-II CPLD is chosen as the target device into which the VHDL circuit description can be synthesized and configured into the CPLD. In addition, a MATLAB script is generated to allow for analysis in MATLAB and a SPICE netlist is generated for analog circuit simulation.
KW - PLD
KW - pulse-frequency modulation
KW - Python
KW - VHDL
UR - http://www.scopus.com/inward/record.url?scp=85066634163&partnerID=8YFLogxK
U2 - 10.1109/IEECON.2018.8712177
DO - 10.1109/IEECON.2018.8712177
M3 - Conference contribution
AN - SCOPUS:85066634163
T3 - iEECON 2018 - 6th International Electrical Engineering Congress
BT - iEECON 2018 - 6th International Electrical Engineering Congress
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th International Electrical Engineering Congress, iEECON 2018
Y2 - 7 March 2018 through 9 March 2018
ER -