Razor based programmable truncated multiply and accumulate, energy-reduction for efficient digital signal processing

Fault tolerant techniques can extend the power savings achievable by dynamic voltage scaling by trading accuracy and/or timing performance against power. Such energy improvements have a strong dependency on the delay distribution of the circuit and the statistical characteristics of the input signal. Independently, programmable truncated multipliers also achieve power benefits at the expense of degradation of the output signal-to-noise ratio. In this brief, a combination of programmable truncated multiplication is used within a fault tolerant digital signal processing (DSP) structure in which the supply voltage is reduced beyond the critical timing level. Timing modulation properties of truncated multiplication are analyzed and demonstrated to improve the performance of fault tolerant designs, reducing error correction burdens, and extending the system operating voltage range. Combining both power strategies results in lower energy consumption levels, which improve the energy savings beyond that expected when applying a combination of both techniques with the original DSP.