Systolic architectures for decoding Reed Solomon codes

John Nelson, Abdur Rahman, Eamonn McQuade

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A systolic implementation of a Reed-Solomon decoder is presented which with minor modification is suitable for BCH and Goppa codes. The various operations involved in decoding such codes were analyzed and the results are described. Systolic array architectures are derived for the various steps including the syndrome calculation, key equation solution and error evaluation. Since the throughput of the decoder is effectively determined by the speed of the multipliers, various multiplier architectures are discussed briefly. The architectures presented improve upon previous designs. The result is highly regular and modular, and thus it is more suitable for VLSI implementation.

Original languageEnglish
Title of host publicationProc 90 Int Conf Appl Specif Array Process
PublisherPubl by IEEE
Pages67-77
Number of pages11
ISBN (Print)0818690895
Publication statusPublished - 1991
EventProceedings of the 1990 International Conference on Application Specific Array Processors - Princeton, NJ, USA
Duration: 5 Sep 19907 Sep 1990

Publication series

NameProc 90 Int Conf Appl Specif Array Process

Conference

ConferenceProceedings of the 1990 International Conference on Application Specific Array Processors
CityPrinceton, NJ, USA
Period5/09/907/09/90

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